KMAC/UNMASKED Simulation Results

Thursday May 15 2025 17:06:21 UTC

GitHub Revision: 38b1fbc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	3.460s	502.354us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.770s	21.711us	1	1	100.00
V1	csr_rw	kmac_csr_rw	2.040s	18.421us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.580s	147.028us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.150s	253.730us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.040s	192.950us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.040s	18.421us	1	1	100.00
		kmac_csr_aliasing	4.150s	253.730us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.570s	12.239us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.010s	63.302us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	17.447m	59.409ms	1	1	100.00
V2	burst_write	kmac_burst_write	6.200m	5.790ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	25.800m	83.579ms	1	1	100.00
		kmac_test_vectors_sha3_256	17.402m	68.881ms	1	1	100.00
		kmac_test_vectors_sha3_384	16.857m	45.029ms	1	1	100.00
		kmac_test_vectors_sha3_512	12.525m	918.265ms	1	1	100.00
		kmac_test_vectors_shake_128	1.947m	13.392ms	1	1	100.00
		kmac_test_vectors_shake_256	3.898m	20.449ms	1	1	100.00
		kmac_test_vectors_kmac	2.500s	36.858us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.480s	85.651us	1	1	100.00
V2	sideload	kmac_sideload	2.145m	2.569ms	1	1	100.00
V2	app	kmac_app	1.788m	2.559ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.216m	6.962ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	36.070s	6.007ms	1	1	100.00
V2	error	kmac_error	2.041m	45.993ms	1	1	100.00
V2	key_error	kmac_key_error	6.150s	3.535ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.720s	2.455ms	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	3.330s	88.411us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	5.390s	93.532us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	32.530s	12.044ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.290s	38.410us	1	1	100.00
V2	stress_all	kmac_stress_all	2.015m	31.406ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.640s	46.655us	1	1	100.00
V2	alert_test	kmac_alert_test	1.820s	49.839us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.430s	53.988us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.430s	53.988us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.770s	21.711us	1	1	100.00
		kmac_csr_rw	2.040s	18.421us	1	1	100.00
		kmac_csr_aliasing	4.150s	253.730us	1	1	100.00
		kmac_same_csr_outstanding	2.060s	652.157us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.770s	21.711us	1	1	100.00
		kmac_csr_rw	2.040s	18.421us	1	1	100.00
		kmac_csr_aliasing	4.150s	253.730us	1	1	100.00
		kmac_same_csr_outstanding	2.060s	652.157us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.380s	79.573us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.380s	79.573us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.380s	79.573us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.380s	79.573us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.130s	786.844us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	27.920s	2.994ms	1	1	100.00
		kmac_tl_intg_err	1.590s	18.994us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.590s	18.994us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.290s	38.410us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	3.460s	502.354us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.145m	2.569ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.380s	79.573us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	27.920s	2.994ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	27.920s	2.994ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	27.920s	2.994ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	3.460s	502.354us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.290s	38.410us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	27.920s	2.994ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.977m	52.247ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	3.460s	502.354us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	33.350s	1.187ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.58294512743854539949355949438330036616568441556269122457142923671826432783603
      Line 95, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1187119001 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 1187119001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.7392994331299840316834772725485619091911020598709883032881481755805673141180
      Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
        UVM_ERROR @  18993771 ps: (kmac_csr_assert_fpv.sv:505) [ASSERT FAILED] prefix_2_rd_A
        UVM_INFO @  18993771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---