38b1fbc| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 40.000s | 1.427ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 8.000s | 66.534us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 8.000s | 43.045us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 5.000s | 104.574us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 3.000s | 22.709us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 4.000s | 2.022us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 8.000s | 43.045us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 3.000s | 22.709us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 42.000s | 35.768ms | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 1.250m | 1.553ms | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 32.000s | 1.291ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 10.000s | 15.302us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 8.000s | 3.278us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 8.000s | 3.278us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 8.000s | 66.534us | 1 | 1 | 100.00 |
| mbx_csr_rw | 8.000s | 43.045us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 3.000s | 22.709us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 3.000s | 31.784us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 8.000s | 66.534us | 1 | 1 | 100.00 |
| mbx_csr_rw | 8.000s | 43.045us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 3.000s | 22.709us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 3.000s | 31.784us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 10.000s | 13.900us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 7.000s | 15.168us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Invalid, value: * a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_errors.77278479276741535962638913542157451953337668893160644897164991535048415665834
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 3278104 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xf3d12a5c a_data = 0x34de1ecf a_mask = 0x3 a_size = 0x2 a_param = 0x0 a_source = 0x63 a_opcode = Invalid, value: 3 a_user = 0x25835 d_data = 0xeca4d69a d_size = 0x3 d_param = 0x0 d_source = 0x4b d_opcode = AccessAckData d_error = 0 d_user = 11011110001010 d_sink = 1 req_abort_after_a_valid_len = 1 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 3278104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Get a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_intg_err.95143372242024202059424104471002868594748373655573920453251143443807069846279
Line 88, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 15167895 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x88497b14 a_data = 0x44a8f5b2 a_mask = 0x6 a_size = 0x2 a_param = 0x0 a_source = 0xba a_opcode = Get a_user = 0x2592a d_data = 0x4e84e3a4 d_size = 0x2 d_param = 0x0 d_source = 0xde d_opcode = AccessAckData d_error = 0 d_user = 10110010010001 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 15167895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutPartialData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_csr_mem_rw_with_rand_reset.36683756905109614126381699282630909816179053032319204547295935645510495227782
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 2021570 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x396699ac a_data = 0x1e4d522f a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0x89 a_opcode = PutPartialData a_user = 0x1b7d1 d_data = 0x8774dfd d_size = 0x2 d_param = 0x0 d_source = 0x2d d_opcode = AccessAck d_error = 0 d_user = 10011010011111 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 2021570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---