OTBN Simulation Results

Thursday May 15 2025 17:06:21 UTC

GitHub Revision: 38b1fbc

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	37.561us	1	1	100.00
V1	single_binary	otbn_single	9.000s	13.512us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	23.935us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	25.708us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	365.644us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	13.873us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	8.000s	44.426us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	25.708us	1	1	100.00
		otbn_csr_aliasing	6.000s	13.873us	1	1	100.00
V1	mem_walk	otbn_mem_walk	21.000s	1.440ms	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	16.000s	555.384us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	19.000s	265.864us	1	1	100.00
V2	multi_error	otbn_multi_err	46.000s	149.282us	1	1	100.00
V2	back_to_back	otbn_multi	1.000m	626.594us	1	1	100.00
V2	stress_all	otbn_stress_all	43.000s	654.628us	1	1	100.00
V2	lc_escalation	otbn_escalate	8.000s	38.170us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	23.362us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	10.000s	25.294us	1	1	100.00
V2	alert_test	otbn_alert_test	6.000s	70.534us	1	1	100.00
V2	intr_test	otbn_intr_test	6.000s	21.386us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	8.000s	61.077us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	8.000s	61.077us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	23.935us	1	1	100.00
		otbn_csr_rw	6.000s	25.708us	1	1	100.00
		otbn_csr_aliasing	6.000s	13.873us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	21.590us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	23.935us	1	1	100.00
		otbn_csr_rw	6.000s	25.708us	1	1	100.00
		otbn_csr_aliasing	6.000s	13.873us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	21.590us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	10.000s	32.192us	1	1	100.00
		otbn_dmem_err	12.000s	74.711us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	9.000s	30.942us	1	1	100.00
		otbn_controller_ispr_rdata_err	9.000s	587.288us	1	1	100.00
		otbn_mac_bignum_acc_err	10.000s	22.516us	1	1	100.00
		otbn_urnd_err	10.000s	25.929us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	12.642us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	22.081us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	19.527us	0	1	0.00
V2S	tl_intg_err	otbn_sec_cm	8.000s	44.282us	0	1	0.00
		otbn_tl_intg_err	20.000s	141.875us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	23.000s	644.500us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	8.000s	44.282us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	8.000s	44.282us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	37.561us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	74.711us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	10.000s	32.192us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	20.000s	141.875us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	8.000s	38.170us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	10.000s	32.192us	1	1	100.00
		otbn_dmem_err	12.000s	74.711us	1	1	100.00
		otbn_zero_state_err_urnd	10.000s	23.362us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	12.642us	1	1	100.00
		otbn_sec_cm	8.000s	44.282us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	8.000s	44.282us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	9.000s	13.512us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	10.000s	32.192us	1	1	100.00
		otbn_dmem_err	12.000s	74.711us	1	1	100.00
		otbn_zero_state_err_urnd	10.000s	23.362us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	12.642us	1	1	100.00
		otbn_sec_cm	8.000s	44.282us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	8.000s	44.282us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	8.000s	38.170us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	10.000s	32.192us	1	1	100.00
		otbn_dmem_err	12.000s	74.711us	1	1	100.00
		otbn_zero_state_err_urnd	10.000s	23.362us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	12.642us	1	1	100.00
		otbn_sec_cm	8.000s	44.282us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	8.000s	44.282us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	9.000s	13.512us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	9.000s	41.443us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	22.435us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	21.000s	783.407us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	21.000s	783.407us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	10.000s	36.797us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	8.000s	44.282us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	8.000s	44.282us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	10.000s	55.368us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	8.000s	44.282us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	8.000s	44.282us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	7.000s	32.933us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	7.000s	32.933us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	9.000s	27.630us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	9.000s	13.512us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	9.000s	13.512us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	9.000s	13.512us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.000m	626.594us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	9.000s	13.512us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	9.000s	13.512us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	9.000s	21.863us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	9.000s	13.512us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	8.000s	44.282us	0	1	0.00
V2S		TOTAL			17	20	85.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	2.183m	720.760us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			38	41	92.68

Failure Buckets

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:

  • Test otbn_sec_wipe_err has 1 failures.

    • 0.otbn_sec_wipe_err.114754317205226978452105025323939394990624407700451226124734199472884631484115
      Line 109, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 27629941 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  27629941 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  27629941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed has 1 failures:

  • Test otbn_partial_wipe has 1 failures.

    • 0.otbn_partial_wipe.85747180819550879442862628432700663570230502850559393268086886613339478455552
      Line 102, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_partial_wipe/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 19526636 PS) Assertion tb.MatchingStatus_A has failed
        UVM_ERROR @  19526636 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
        UVM_INFO @  19526636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

  • Test otbn_sec_cm has 1 failures.

    • 0.otbn_sec_cm.26939633002977338065006820896910645651117780524915301951024976820524215951435
      Line 96, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 44282124 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 44282124 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @  44282124 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @  44282124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---