ROM_CTRL/32KB Simulation Results

Thursday May 15 2025 17:06:21 UTC

GitHub Revision: 38b1fbc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.070s 1.687ms 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 6.190s 605.270us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.400s 731.301us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 5.490s 178.274us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.270s 557.408us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 4.830s 566.691us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.400s 731.301us 1 1 100.00
rom_ctrl_csr_aliasing 4.270s 557.408us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 3.610s 416.790us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.610s 212.145us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 4.860s 138.875us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 12.140s 458.133us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 9.130s 302.072us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.240s 148.338us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.490s 333.588us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.490s 333.588us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 6.190s 605.270us 1 1 100.00
rom_ctrl_csr_rw 4.400s 731.301us 1 1 100.00
rom_ctrl_csr_aliasing 4.270s 557.408us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.530s 540.312us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 6.190s 605.270us 1 1 100.00
rom_ctrl_csr_rw 4.400s 731.301us 1 1 100.00
rom_ctrl_csr_aliasing 4.270s 557.408us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.530s 540.312us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.227m 3.495ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 17.780s 4.940ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.971m 685.983us 1 1 100.00
rom_ctrl_tl_intg_err 25.580s 252.921us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.971m 685.983us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.971m 685.983us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.227m 3.495ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.227m 3.495ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.227m 3.495ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.227m 3.495ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.227m 3.495ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.971m 685.983us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.971m 685.983us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.070s 1.687ms 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.070s 1.687ms 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.070s 1.687ms 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 25.580s 252.921us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.227m 3.495ms 1 1 100.00
rom_ctrl_kmac_err_chk 9.130s 302.072us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.227m 3.495ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.227m 3.495ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.227m 3.495ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 17.780s 4.940ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.971m 685.983us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 43.370s 7.713ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00