ROM_CTRL/64KB Simulation Results

Thursday May 15 2025 17:06:21 UTC

GitHub Revision: 38b1fbc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.540s 557.705us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 7.600s 703.128us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 8.610s 1.026ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 5.810s 1.139ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 8.700s 305.758us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.170s 1.820ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 8.610s 1.026ms 1 1 100.00
rom_ctrl_csr_aliasing 8.700s 305.758us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.790s 210.244us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.640s 415.014us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.980s 228.470us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 17.780s 1.089ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 15.470s 570.603us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.670s 726.350us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.030s 211.124us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.030s 211.124us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 7.600s 703.128us 1 1 100.00
rom_ctrl_csr_rw 8.610s 1.026ms 1 1 100.00
rom_ctrl_csr_aliasing 8.700s 305.758us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.740s 371.929us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 7.600s 703.128us 1 1 100.00
rom_ctrl_csr_rw 8.610s 1.026ms 1 1 100.00
rom_ctrl_csr_aliasing 8.700s 305.758us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.740s 371.929us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.807m 3.625ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 37.890s 6.395ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 5.296m 2.157ms 1 1 100.00
rom_ctrl_tl_intg_err 40.240s 705.171us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 5.296m 2.157ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 5.296m 2.157ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.807m 3.625ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.807m 3.625ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.807m 3.625ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.807m 3.625ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.807m 3.625ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 5.296m 2.157ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 5.296m 2.157ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.540s 557.705us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.540s 557.705us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.540s 557.705us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 40.240s 705.171us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.807m 3.625ms 1 1 100.00
rom_ctrl_kmac_err_chk 15.470s 570.603us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.807m 3.625ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.807m 3.625ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.807m 3.625ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 37.890s 6.395ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 5.296m 2.157ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.118m 5.305ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00