RV_TIMER Simulation Results

Thursday May 15 2025 17:06:21 UTC

GitHub Revision: 38b1fbc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.690s	20.696us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.720s	39.803us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.540s	44.396us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.380s	2.747ms	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.510s	35.336us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.950s	39.786us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.540s	44.396us	1	1	100.00
		rv_timer_csr_aliasing	1.510s	35.336us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.770s	1.292ms	1	1	100.00
V2	disabled	rv_timer_disabled	2.830s	1.307ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	16.920s	13.430ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	16.920s	13.430ms	1	1	100.00
V2	stress	rv_timer_stress_all	1.450s	65.855us	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.420s	38.419us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.570s	100.005us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.340s	36.824us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.340s	36.824us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.720s	39.803us	1	1	100.00
		rv_timer_csr_rw	1.540s	44.396us	1	1	100.00
		rv_timer_csr_aliasing	1.510s	35.336us	1	1	100.00
		rv_timer_same_csr_outstanding	1.610s	19.489us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.720s	39.803us	1	1	100.00
		rv_timer_csr_rw	1.540s	44.396us	1	1	100.00
		rv_timer_csr_aliasing	1.510s	35.336us	1	1	100.00
		rv_timer_same_csr_outstanding	1.610s	19.489us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.580s	67.663us	1	1	100.00
		rv_timer_tl_intg_err	1.940s	84.683us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.940s	84.683us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	21.010s	3.357ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.830s	18.879us	1	1	100.00
		rv_timer_max	1.630s	48.035us	1	1	100.00
		TOTAL			19	19	100.00