SPI_DEVICE/1R1W Simulation Results

Thursday May 15 2025 17:06:21 UTC

GitHub Revision: 38b1fbc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	50.530s	9.784ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.860s	120.948us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.600s	279.348us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.670s	2.437ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.430s	755.802us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.550s	134.482us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.600s	279.348us	1	1	100.00
		spi_device_csr_aliasing	11.430s	755.802us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	2.070s	20.487us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.970s	114.753us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	2.040s	24.388us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.810s	1.635us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.770s	3.368us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	3.140s	185.525us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	3.140s	185.525us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.620s	536.921us	1	1	100.00
		spi_device_tpm_sts_read	1.800s	117.467us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	8.230s	1.448ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	9.440s	10.103ms	1	1	100.00
		spi_device_flash_all	16.280s	14.349ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.240s	115.375us	1	1	100.00
		spi_device_flash_all	16.280s	14.349ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.240s	115.375us	1	1	100.00
		spi_device_flash_all	16.280s	14.349ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	16.280s	14.349ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	15.180s	8.240ms	1	1	100.00
		spi_device_flash_all	16.280s	14.349ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	15.180s	8.240ms	1	1	100.00
		spi_device_flash_all	16.280s	14.349ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	15.180s	8.240ms	1	1	100.00
		spi_device_flash_all	16.280s	14.349ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	15.180s	8.240ms	1	1	100.00
		spi_device_flash_all	16.280s	14.349ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	15.180s	8.240ms	1	1	100.00
		spi_device_flash_all	16.280s	14.349ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	6.010s	6.239ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	3.010s	57.105us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.010s	57.105us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.010s	57.105us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	12.510s	1.014ms	1	1	100.00
		spi_device_read_buffer_direct	4.970s	414.095us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.010s	57.105us	1	1	100.00
		spi_device_flash_all	16.280s	14.349ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	16.280s	14.349ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	16.280s	14.349ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.350s	754.496us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.350s	754.496us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	50.530s	9.784ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	3.436m	134.841ms	1	1	100.00
V2	stress_all	spi_device_stress_all	3.417m	47.914ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.590s	13.558us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.610s	25.400us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.700s	123.012us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.700s	123.012us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.860s	120.948us	1	1	100.00
		spi_device_csr_rw	2.600s	279.348us	1	1	100.00
		spi_device_csr_aliasing	11.430s	755.802us	1	1	100.00
		spi_device_same_csr_outstanding	4.270s	215.903us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.860s	120.948us	1	1	100.00
		spi_device_csr_rw	2.600s	279.348us	1	1	100.00
		spi_device_csr_aliasing	11.430s	755.802us	1	1	100.00
		spi_device_same_csr_outstanding	4.270s	215.903us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.050s	210.759us	1	1	100.00
		spi_device_tl_intg_err	6.490s	341.545us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.490s	341.545us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	39.650s	134.795ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.39014006887213781870480821119466211146039997076385359413153285261875575793277
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1166557 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[12])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1166557 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1166557 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[908])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.33647430725720741751330925360549137829653028599992321652127700095852288380421
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    844296 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x582037 [10110000010000000110111] vs 0x0 [0])
        UVM_ERROR @    888296 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x16fb10 [101101111101100010000] vs 0x0 [0])
        UVM_ERROR @    940296 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x77d9f7 [11101111101100111110111] vs 0x0 [0])
        UVM_ERROR @    989296 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8174bd [100000010111010010111101] vs 0x0 [0])
        UVM_ERROR @   1061296 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x72e73c [11100101110011100111100] vs 0x0 [0])