SRAM_CTRL/MAIN Simulation Results

Thursday May 15 2025 17:06:21 UTC

GitHub Revision: 38b1fbc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	15.070s	8.915ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.570s	43.705us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.620s	22.272us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.980s	73.226us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.600s	12.234us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.850s	2.674ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.620s	22.272us	1	1	100.00
		sram_ctrl_csr_aliasing	1.600s	12.234us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.897m	17.750ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.663m	12.076ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	4.412m	26.011ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.450m	34.581ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	12.148m	28.934ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	9.949m	35.345ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	34.820s	8.198ms	1	1	100.00
V2	executable	sram_ctrl_executable	14.190m	105.693ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	14.730s	1.654ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.539m	119.157ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	51.610s	802.256us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	20.410s	3.336ms	1	1	100.00
		sram_ctrl_throughput_w_readback	19.670s	979.292us	1	1	100.00
V2	regwen	sram_ctrl_regwen	4.713m	11.995ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.620s	708.682us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	29.185m	176.931ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.730s	12.103us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.250s	66.735us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.250s	66.735us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.570s	43.705us	1	1	100.00
		sram_ctrl_csr_rw	1.620s	22.272us	1	1	100.00
		sram_ctrl_csr_aliasing	1.600s	12.234us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.980s	29.002us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.570s	43.705us	1	1	100.00
		sram_ctrl_csr_rw	1.620s	22.272us	1	1	100.00
		sram_ctrl_csr_aliasing	1.600s	12.234us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.980s	29.002us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	29.820s	7.391ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.520s	3.677us	0	1	0.00
		sram_ctrl_tl_intg_err	2.150s	115.041us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.520s	3.677us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.150s	115.041us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	4.713m	11.995ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	4.713m	11.995ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.620s	22.272us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	14.190m	105.693ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	14.190m	105.693ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	14.190m	105.693ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	34.820s	8.198ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.620s	3.026ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	29.820s	7.391ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.640s	1.353ms	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	15.070s	8.915ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	15.070s	8.915ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	14.190m	105.693ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.520s	3.677us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	34.820s	8.198ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.520s	3.677us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.520s	3.677us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	15.070s	8.915ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.520s	3.677us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	21.090s	1.117ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.93584996592368994558181396236744177440910286385843103945338893945057764263510
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 1352979873 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x47) != exp (0xf)
        UVM_INFO @ 1352979873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_opcode === ((pend_req[d2h.d_source].opcode == Get) ? AccessAckData : AccessAck))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.101139869578645136597462278462521724138360164380858148075491240367963359723406
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === ((pend_req[d2h.d_source].opcode == Get) ? AccessAckData : AccessAck))'
        UVM_ERROR @   3676856 ps: (tlul_assert.sv:273) [ASSERT FAILED] respOpcode_A
        UVM_INFO @   3676856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---