SRAM_CTRL/RET Simulation Results

Thursday May 15 2025 17:06:21 UTC

GitHub Revision: 38b1fbc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	34.170s	1.120ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.190s	199.584us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.630s	24.032us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.760s	1.046ms	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.420s	45.028us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.180s	121.084us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.630s	24.032us	1	1	100.00
		sram_ctrl_csr_aliasing	1.420s	45.028us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.690s	1.509ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.170s	46.483us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	16.846m	27.586ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.216m	2.015ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	31.920s	1.945ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	15.394m	19.877ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.750s	639.009us	1	1	100.00
V2	executable	sram_ctrl_executable	6.418m	13.283ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	10.250s	1.634ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.127m	68.533ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	4.630s	180.059us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	3.400s	159.324us	1	1	100.00
		sram_ctrl_throughput_w_readback	30.540s	229.851us	1	1	100.00
V2	regwen	sram_ctrl_regwen	1.870m	21.496ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.800s	28.898us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	36.701m	73.448ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.650s	14.513us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.360s	40.612us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.360s	40.612us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.190s	199.584us	1	1	100.00
		sram_ctrl_csr_rw	1.630s	24.032us	1	1	100.00
		sram_ctrl_csr_aliasing	1.420s	45.028us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.610s	228.325us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.190s	199.584us	1	1	100.00
		sram_ctrl_csr_rw	1.630s	24.032us	1	1	100.00
		sram_ctrl_csr_aliasing	1.420s	45.028us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.610s	228.325us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.460s	222.966us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.670s	7.065us	0	1	0.00
		sram_ctrl_tl_intg_err	2.750s	644.613us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.670s	7.065us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.750s	644.613us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	1.870m	21.496ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	1.870m	21.496ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.630s	24.032us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	6.418m	13.283ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	6.418m	13.283ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	6.418m	13.283ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.750s	639.009us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.030s	48.163us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.460s	222.966us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.000s	51.098us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	34.170s	1.120ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	34.170s	1.120ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	6.418m	13.283ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.670s	7.065us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.750s	639.009us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.670s	7.065us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.670s	7.065us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	34.170s	1.120ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.670s	7.065us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.032m	3.304ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.91871779968662014273428491865525784942510357056654419784221351259680504832805
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7065049 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7065049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---