UART Simulation Results

Thursday May 15 2025 17:06:21 UTC

GitHub Revision: 38b1fbc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.960s	490.729us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.580s	14.069us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.660s	37.859us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.740s	114.230us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.670s	48.228us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.830s	114.588us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.660s	37.859us	1	1	100.00
		uart_csr_aliasing	1.670s	48.228us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	55.460s	121.007ms	1	1	100.00
V2	parity	uart_smoke	1.960s	490.729us	1	1	100.00
		uart_tx_rx	55.460s	121.007ms	1	1	100.00
V2	parity_error	uart_intr	9.630s	22.166ms	1	1	100.00
		uart_rx_parity_err	28.100s	103.702ms	1	1	100.00
V2	watermark	uart_tx_rx	55.460s	121.007ms	1	1	100.00
		uart_intr	9.630s	22.166ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.348m	248.561ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	43.840s	42.801ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	44.670s	36.393ms	1	1	100.00
V2	rx_frame_err	uart_intr	9.630s	22.166ms	1	1	100.00
V2	rx_break_err	uart_intr	9.630s	22.166ms	1	1	100.00
V2	rx_timeout	uart_intr	9.630s	22.166ms	1	1	100.00
V2	perf	uart_perf	2.257m	7.516ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.480s	1.243ms	1	1	100.00
V2	line_loopback	uart_loopback	2.480s	1.243ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.268m	77.671ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.800s	2.100ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.070s	997.206us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	15.070s	3.169ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	4.538m	52.682ms	1	1	100.00
V2	stress_all	uart_stress_all	2.849m	315.348ms	1	1	100.00
V2	alert_test	uart_alert_test	1.950s	13.867us	1	1	100.00
V2	intr_test	uart_intr_test	1.600s	55.575us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.830s	56.660us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.830s	56.660us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.580s	14.069us	1	1	100.00
		uart_csr_rw	1.660s	37.859us	1	1	100.00
		uart_csr_aliasing	1.670s	48.228us	1	1	100.00
		uart_same_csr_outstanding	1.710s	28.407us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.580s	14.069us	1	1	100.00
		uart_csr_rw	1.660s	37.859us	1	1	100.00
		uart_csr_aliasing	1.670s	48.228us	1	1	100.00
		uart_same_csr_outstanding	1.710s	28.407us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.810s	77.952us	1	1	100.00
		uart_tl_intg_err	2.100s	534.222us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.100s	534.222us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	7.350s	696.089us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00