CHIP Simulation Results

Thursday May 15 2025 17:06:21 UTC

GitHub Revision: `38b1fbc`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.007m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.007m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.639m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.558m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.499m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.708m	5.630ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.708m	5.630ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.708m	5.630ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	38.020s	10.200us	0	1	0.00
		chip_sw_example_manufacturer	2.191m		0	1	0.00
		chip_sw_example_concurrency	3.878m	3.261ms	1	1	100.00
		chip_sw_uart_smoketest_signed	14.274s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	9.870s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	10.830s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	10.830s		0	1	0.00
V1	xbar_smoke	xbar_smoke	18.320s	57.872us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.910m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	8.360m	8.243ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	5.278m	4.489ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	53.280s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	54.686s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.493m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	1.233m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.590s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.590s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.023m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.986m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.017m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.017m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.885m	4.796ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.923m	3.096ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.622m	14.949ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.843s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.514s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.576m	11.435ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.223m	5.078ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	22.647m	18.017ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	22.647m	18.017ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.580s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.731m	4.482ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.731m	4.482ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	7.045m	18.016ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.655m	4.459ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.316m	4.001ms	1	1	100.00
		chip_sw_aes_idle	4.179m	4.471ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.474m	3.376ms	1	1	100.00
		chip_sw_kmac_idle	3.520m	4.383ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	12.350m	12.021ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	11.477m	12.015ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	11.939m	12.017ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	11.247m	12.021ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	13.792s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.385s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.121s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.291s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.142s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.802s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.335s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	13.792s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.385s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.121s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.291s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.142s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.802s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.335s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.230s		0	1	0.00
		chip_sw_aes_enc_jitter_en	1.383m	10.100us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	46.770s	10.320us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	48.470s	10.220us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	48.570s	10.360us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.064s		0	1	0.00
		chip_sw_clkmgr_jitter	4.196m	5.787ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.171m	3.532ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	13.022s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	55.790s	10.140us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	48.260s	10.340us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	46.640s	10.360us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	46.600s	10.240us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	1.059m	10.100us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	14.790s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.742s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.626s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	10.621s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	18.034m	13.858ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.221m	12.857ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.731m	4.482ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	16.160s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.221m	12.857ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	39.622s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	17.705s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	26.125s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	42.055s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	37.351s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	18.034m	13.858ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.622m	14.949ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	20.675m	20.020ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.284m	6.431ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	9.330m	10.083ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.317m	3.845ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	18.034m	13.858ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	13.012s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	12.026s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	18.034m	13.858ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	11.069s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	9.330m	10.083ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	12.034s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	10.967s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.662s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.729s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	10.712s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	10.968s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	12.026s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	12.338s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	11.982s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	12.338s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	12.338s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	12.338s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	8.941m	9.206ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	15.645s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	19.818s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	31.920s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	18.442s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.338s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.469m	8.859ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	9.970m	12.262ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.495s		0	1	0.00
		chip_prim_tl_access	8.173m	17.951ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	13.792s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.385s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.121s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.291s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.142s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.802s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.335s		0	1	0.00
		chip_rv_dm_lc_disabled	6.576m	11.435ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.186m	4.605ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.383m	10.100us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.688m	4.385ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.179m	4.471ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.807m	5.088ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	46.770s	10.320us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.474m	3.376ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.635m	5.608ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.846m	5.442ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	48.570s	10.360us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.469m	8.859ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	12.338s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	41.940s	10.100us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.743m	5.130ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.520m	4.383ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	14.369s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	14.369s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.413s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.051m	3.772ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.128s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.469m	8.859ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	48.470s	10.220us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	10.852s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	12.230s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.316m	4.001ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.316m	4.001ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.316m	4.001ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.005m	6.388ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.970m	12.262ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.970m	12.262ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.760m	10.582ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.064s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.495s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	18.034m	13.858ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.017m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	12.338s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.005m	6.388ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.469m	8.859ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.760m	10.582ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.570m	4.354ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.005m	6.388ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.469m	8.859ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.760m	10.582ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.570m	4.354ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	12.338s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.586s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	11.982s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	15.645s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	19.818s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	31.920s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	18.442s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.338s		0	1	0.00
		chip_prim_tl_access	8.173m	17.951ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	8.173m	17.951ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	13.635s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	38.908s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.742s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.230s		0	1	0.00
		chip_sw_aes_enc_jitter_en	1.383m	10.100us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	46.770s	10.320us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	48.470s	10.220us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	48.570s	10.360us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.064s		0	1	0.00
		chip_sw_clkmgr_jitter	4.196m	5.787ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	8.384m	10.248ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	8.384m	10.248ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.255m	4.958ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.706m	4.696ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.527m	4.439ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.344m	4.973ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.939m	5.495ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.872m	3.545ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.570m	4.354ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	20.675m	20.020ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	20.675m	20.020ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.299m	3.510ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.031m	3.716ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.085m	5.320ms	1	1	100.00
		chip_sw_csrng_smoketest	3.252m	4.395ms	1	1	100.00
		chip_sw_gpio_smoketest	3.964m	4.101ms	1	1	100.00
		chip_sw_hmac_smoketest	3.876m	4.049ms	1	1	100.00
		chip_sw_kmac_smoketest	3.673m	4.147ms	1	1	100.00
		chip_sw_otbn_smoketest	5.397m	4.904ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.603m	5.129ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.238m	4.034ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.167m	4.359ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.610m	3.920ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.116m	2.971ms	1	1	100.00
		chip_sw_uart_smoketest	3.837m	4.501ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	14.397s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	14.274s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.910m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	14.656s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.220m	5.025ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.900m	6.545ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.240m	5.133ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.938m	6.236ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	11.313s		0	1	0.00
		chip_rv_dm_lc_disabled	6.576m	11.435ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	22.592s		0	1	0.00
		chip_sw_lc_walkthrough_prod	16.648s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	23.123s		0	1	0.00
		chip_sw_lc_walkthrough_rma	12.024s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	11.313s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	42.116s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	16.537s		0	1	0.00
		rom_volatile_raw_unlock	10.834s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.990s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.783m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.847m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.558m	3.612ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.558m	3.612ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	10.830s		0	1	0.00
		chip_same_csr_outstanding	13.130s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	10.830s		0	1	0.00
		chip_same_csr_outstanding	13.130s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	3.257m	598.280us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	12.530s	11.561us	1	1	100.00
		xbar_smoke_large_delays	3.864m	2.071ms	1	1	100.00
		xbar_smoke_slow_rsp	4.689m	1.812ms	1	1	100.00
		xbar_random_zero_delays	41.590s	41.918us	1	1	100.00
		xbar_random_large_delays	6.961m	3.688ms	1	1	100.00
		xbar_random_slow_rsp	20.076m	7.503ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	29.700s	52.954us	1	1	100.00
		xbar_error_and_unmapped_addr	21.190s	15.481us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	47.400s	58.265us	1	1	100.00
		xbar_error_and_unmapped_addr	21.190s	15.481us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	3.200m	482.658us	1	1	100.00
		xbar_access_same_device_slow_rsp	52.761m	21.381ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	32.110s	100.926us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.418m	165.462us	1	1	100.00
		xbar_stress_all_with_error	1.348m	270.703us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	18.685m	703.859us	1	1	100.00
		xbar_stress_all_with_reset_error	5.972m	310.749us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.993s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.266s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.427s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.241s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	11.902s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	12.080s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.521s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	10.847s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.595s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.093s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.261s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.133s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.388s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	12.520s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.357s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	12.363s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.994s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	11.674s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	12.387s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.017s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	12.834s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	13.472s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	12.044s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	13.036s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.425s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.411s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.157s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	11.751s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.895s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.720s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	11.655s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.144s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.215s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.957s		0	1	0.00
		rom_e2e_asm_init_dev	12.530s		0	1	0.00
		rom_e2e_asm_init_prod	12.015s		0	1	0.00
		rom_e2e_asm_init_prod_end	12.158s		0	1	0.00
		rom_e2e_asm_init_rma	10.886s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.972s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.120s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.067s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	12.787s		0	1	0.00
V2		TOTAL			65	205	31.71
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.453m	5.255ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.429m	5.297ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.910s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.138s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.004s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.007s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	18.034m	13.858ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	24.303s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	18.454m	14.458ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	10.933s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	14.696s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.910s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.138s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.004s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	10.973s		0	1	0.00
		rom_e2e_jtag_inject_dev	12.208s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.284s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.104m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	18.399m	14.900ms	1	1	100.00
		chip_plic_all_irqs_0	9.107m	5.886ms	1	1	100.00
		chip_plic_all_irqs_10	10.004m	6.021ms	1	1	100.00
		chip_sw_dma_inline_hashing	3.884m	5.046ms	1	1	100.00
		chip_sw_dma_abort	4.233m	3.389ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.865s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.153s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	10.964s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	12.102s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.881s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.307s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.886s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.480s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.301s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.566s		0	1	0.00
		chip_sw_mbx_smoketest	3.999m	5.054ms	1	1	100.00
		TOTAL			76	247	30.77

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.4006843223760266619877161788227705974765967724997671692800880294084786372518
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (1 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (f4bbea)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 118.711s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.51853123756823800059432934577680238562587184094975618265323769776826040750219
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (3d5954)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 110.556s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.83392449023879480878863162747289909509304301169282071047822366012954986864897
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (abf100)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 110.191s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.60398498859512816398313516585963775188062844828567988368909386389154653467346
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (3467be)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 108.683s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.66091079747976959938614059670786817966473541126601053902785728817973223810779
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (bd0272)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 108.675s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.115719068067924058390713084153351119668620112064832456309711666298583478634061
    Line 411, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.108015801596292846254095012674863064539838244633879386120634657942289922542440
    Line 435, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.82185828943742172184346554329102917592994658215978133086292127356526982601558
    Line 419, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.110626593528967753332810469560677693863588448659700014404548855077541303869578
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.73561300589369489313319390381301675692811778525512418191733975964826798152106
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 5 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.108002272014834977211105587376038561557316302114724361470650012275557407054934
Line 483, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20020.139772 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20020.139772 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.29891781997885970426929623278431363227214536907630582618175210379869094131792
Line 456, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18017.220026 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18017.220026 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.27530538331625132458367670937378302456933618574548057251608941707797878208475
Line 456, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18016.016200 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18016.016200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.57974350415863492039785299386582894114469640343091468087554136451826789982558
Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12014.596949 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12014.596949 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.93980556959790513415560388129018601418773483850627706324854962170606061152362
Line 418, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12016.840400 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12016.840400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.1990219694733760236515028553969561568156884219287315743990851620233622874611
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.7760003063809005004921760514071137470787055593796140229010492540215169213788
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.84350068992116284001176910666171190509713090742784730684529272617357712326029
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.37611194232489640259456777614046872760587149183403774526088603594707800140685
Line 475, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 8859.106556 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (54780581334934847675808791790717204314379261681754593844669492440719512481913 [0x791cb5d441fa856be9a06d6cb6e25d38785274892f39fe8c47975ceb984eb079] vs 64595411302070889922411494866717163754934411591310386723619063648625425711059 [0x8ecfb5091408453fa7769b4f9671d589fd3ceb566d232378f4e3c0955b9cffd3])
  UVM_INFO @ 8859.106556 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.24462525865357509823060919257013577545310305387005226066293933396476223743427
Line 472, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 9206.451592 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (10409312971817691539346448249843357569261485164777850910366835872214464304097 [0x1703765cfeb60dd8584e834841d86a046f3272fb78525e2f666953401c7b93e1] vs 45373461933537673191145326034500186682171469666309736316893377103457621064890 [0x64507828d18f73f06f7ffccb522a620fb055f703dafde5860e7018a5e0673cba])
  UVM_INFO @ 9206.451592 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 2 failures:
- Test chip_sw_clkmgr_off_aes_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_aes_trans.13297855964058204784709277837114933418576100065537148974494203518692714663911
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log
```
  UVM_ERROR @ 12020.849695 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12020.849695 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_otbn_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_otbn_trans.62020089473925269332538328353921622158633250445724414471355575917846842542611
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log
```
  UVM_ERROR @ 12021.069391 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12021.069391 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.24708115624310246909302330276901702822838231498360434373742542736319726398036
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4796.309553 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h16de5f20  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h5  a_opcode: 'h0  a_user: 'h26949  d_param: 'h0  d_source: 'h5  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4796.309553 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.93426570264808482627390913890560804376444629955150550141295668247280734299147
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3096.043654 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h710ac55b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h34  a_opcode: 'h0  a_user: 'h26974  d_param: 'h0  d_source: 'h34  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3096.043654 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.4717257988589412033359305862549976824767134085172705321352546963289882164448
    Line 582, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.40770592374310063633883716883636294631483191453355508822379022747948433494255
    Line 479, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4488.722488 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4488.722488 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.20398810910898040894960228372028142463231561450438307611365706563309586490375
    Line 744, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 10083.362408 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 10083.362408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.67267770489965624678605909225137344887751121128486784402959993296868181140464
    Line 456, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 4957.687902 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4957.687902 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.64213697804777382052191941960403734695945644344811402038583481294752567358180
    Line 446, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4696.492296 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4696.492296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.2479102907680596090913114844209668308404865243634494429216866590037888674987
    Line 440, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4481.601360 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4481.601360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.107056376598352630581336941845796811682788873591190288867187377940994313667498
    Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 4973.495240 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 4973.495240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.23104608233046491010282071738998397456539282320052599062587847855123895880309
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.8936782440344117249072626789232296720599727438479707679757140419946304097734
    Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3612.006116 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3612.006116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.112639542681155598631027017479674666366725406262703893390379896731343562994152
    Line 401, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14949.217332 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14949.217332 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.107980435465637091100551149059180259566459712269326043720321312110734341858388
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.107661138157137060049769006301064896160087487784986376316226819611949242040746
    Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 3388.680816 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 3388.680816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```