DMA Simulation Results

Monday May 19 2025 17:04:48 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	9.000s	483.407us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	8.000s	314.881us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	7.000s	315.367us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	5.000s	32.878us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	106.403us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	12.000s	2.584ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	8.000s	561.333us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	94.706us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	106.403us	1	1	100.00
		dma_csr_aliasing	8.000s	561.333us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.317m	31.900ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	19.400m	712.716ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	3.150m	32.383ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	2.233m	10.920ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	19.400m	712.716ms	1	1	100.00
V2	dma_abort	dma_abort	9.000s	1.197ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.650m	10.741ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	17.867us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	6.000s	180.654us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	6.000s	180.654us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	5.000s	32.878us	1	1	100.00
		dma_csr_rw	4.000s	106.403us	1	1	100.00
		dma_csr_aliasing	8.000s	561.333us	1	1	100.00
		dma_same_csr_outstanding	4.000s	155.237us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	5.000s	32.878us	1	1	100.00
		dma_csr_rw	4.000s	106.403us	1	1	100.00
		dma_csr_aliasing	8.000s	561.333us	1	1	100.00
		dma_same_csr_outstanding	4.000s	155.237us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	32.000s	74.818us	1	1	100.00
		dma_generic_stress	2.233m	10.920ms	1	1	100.00
		dma_handshake_stress	19.400m	712.716ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	5.000s	352.759us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.883m	24.138ms	1	1	100.00
		dma_longer_transfer	6.000s	528.520us	1	1	100.00
		TOTAL			21	21	100.00