EDN Simulation Results

Monday May 19 2025 17:04:48 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.650s 53.417us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.630s 14.078us 1 1 100.00
V1 csr_rw edn_csr_rw 1.640s 198.893us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.090s 263.705us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 2.160s 74.336us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.890s 92.666us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.640s 198.893us 1 1 100.00
edn_csr_aliasing 2.160s 74.336us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.980s 65.879us 1 1 100.00
V2 csrng_commands edn_genbits 1.980s 65.879us 1 1 100.00
V2 genbits edn_genbits 1.980s 65.879us 1 1 100.00
V2 interrupts edn_intr 1.840s 25.561us 1 1 100.00
V2 alerts edn_alert 1.770s 51.454us 1 1 100.00
V2 errs edn_err 1.900s 19.472us 1 1 100.00
V2 disable edn_disable 1.600s 24.481us 1 1 100.00
edn_disable_auto_req_mode 1.640s 58.865us 1 1 100.00
V2 stress_all edn_stress_all 4.790s 523.505us 1 1 100.00
V2 intr_test edn_intr_test 1.650s 26.266us 1 1 100.00
V2 alert_test edn_alert_test 1.760s 63.686us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.750s 242.521us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.750s 242.521us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.630s 14.078us 1 1 100.00
edn_csr_rw 1.640s 198.893us 1 1 100.00
edn_csr_aliasing 2.160s 74.336us 1 1 100.00
edn_same_csr_outstanding 1.810s 17.789us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.630s 14.078us 1 1 100.00
edn_csr_rw 1.640s 198.893us 1 1 100.00
edn_csr_aliasing 2.160s 74.336us 1 1 100.00
edn_same_csr_outstanding 1.810s 17.789us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 4.570s 1.106ms 1 1 100.00
edn_tl_intg_err 2.880s 206.566us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.610s 41.492us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.770s 51.454us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 4.570s 1.106ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 4.570s 1.106ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 4.570s 1.106ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 4.570s 1.106ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.770s 51.454us 1 1 100.00
edn_sec_cm 4.570s 1.106ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.770s 51.454us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.880s 206.566us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets