HMAC Simulation Results

Monday May 19 2025 17:04:48 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 6.290s 161.000us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.690s 31.890us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.650s 295.627us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 7.630s 773.401us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.320s 680.502us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.880s 22.671us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.650s 295.627us 1 1 100.00
hmac_csr_aliasing 5.320s 680.502us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 34.610s 3.679ms 1 1 100.00
V2 back_pressure hmac_back_pressure 34.910s 3.868ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 9.110s 583.067us 1 1 100.00
hmac_test_sha384_vectors 19.740s 224.714us 1 1 100.00
hmac_test_sha512_vectors 19.510s 512.985us 1 1 100.00
hmac_test_hmac256_vectors 9.300s 1.229ms 1 1 100.00
hmac_test_hmac384_vectors 11.220s 358.061us 1 1 100.00
hmac_test_hmac512_vectors 12.390s 378.268us 1 1 100.00
V2 burst_wr hmac_burst_wr 10.880s 2.731ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 9.986m 4.698ms 1 1 100.00
V2 error hmac_error 33.370s 2.959ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 25.050s 714.602us 1 1 100.00
V2 save_and_restore hmac_smoke 6.290s 161.000us 1 1 100.00
hmac_long_msg 34.610s 3.679ms 1 1 100.00
hmac_back_pressure 34.910s 3.868ms 1 1 100.00
hmac_datapath_stress 9.986m 4.698ms 1 1 100.00
hmac_burst_wr 10.880s 2.731ms 1 1 100.00
hmac_stress_all 1.144m 11.061ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 6.290s 161.000us 1 1 100.00
hmac_long_msg 34.610s 3.679ms 1 1 100.00
hmac_back_pressure 34.910s 3.868ms 1 1 100.00
hmac_datapath_stress 9.986m 4.698ms 1 1 100.00
hmac_wipe_secret 25.050s 714.602us 1 1 100.00
hmac_test_sha256_vectors 9.110s 583.067us 1 1 100.00
hmac_test_sha384_vectors 19.740s 224.714us 1 1 100.00
hmac_test_sha512_vectors 19.510s 512.985us 1 1 100.00
hmac_test_hmac256_vectors 9.300s 1.229ms 1 1 100.00
hmac_test_hmac384_vectors 11.220s 358.061us 1 1 100.00
hmac_test_hmac512_vectors 12.390s 378.268us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 6.290s 161.000us 1 1 100.00
hmac_long_msg 34.610s 3.679ms 1 1 100.00
hmac_back_pressure 34.910s 3.868ms 1 1 100.00
hmac_datapath_stress 9.986m 4.698ms 1 1 100.00
hmac_burst_wr 10.880s 2.731ms 1 1 100.00
hmac_error 33.370s 2.959ms 1 1 100.00
hmac_wipe_secret 25.050s 714.602us 1 1 100.00
hmac_test_sha256_vectors 9.110s 583.067us 1 1 100.00
hmac_test_sha384_vectors 19.740s 224.714us 1 1 100.00
hmac_test_sha512_vectors 19.510s 512.985us 1 1 100.00
hmac_test_hmac256_vectors 9.300s 1.229ms 1 1 100.00
hmac_test_hmac384_vectors 11.220s 358.061us 1 1 100.00
hmac_test_hmac512_vectors 12.390s 378.268us 1 1 100.00
hmac_stress_all 1.144m 11.061ms 1 1 100.00
V2 stress_all hmac_stress_all 1.144m 11.061ms 1 1 100.00
V2 alert_test hmac_alert_test 1.540s 13.152us 1 1 100.00
V2 intr_test hmac_intr_test 1.420s 44.762us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.580s 175.465us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.580s 175.465us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.690s 31.890us 1 1 100.00
hmac_csr_rw 1.650s 295.627us 1 1 100.00
hmac_csr_aliasing 5.320s 680.502us 1 1 100.00
hmac_same_csr_outstanding 3.150s 231.153us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.690s 31.890us 1 1 100.00
hmac_csr_rw 1.650s 295.627us 1 1 100.00
hmac_csr_aliasing 5.320s 680.502us 1 1 100.00
hmac_same_csr_outstanding 3.150s 231.153us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.740s 37.976us 1 1 100.00
hmac_tl_intg_err 4.220s 261.655us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.220s 261.655us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 6.290s 161.000us 1 1 100.00
V3 stress_reset hmac_stress_reset 4.150s 186.329us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 5.021m 5.791ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.640s 21.975us 1 1 100.00
TOTAL 28 28 100.00