I2C Simulation Results

Monday May 19 2025 17:04:48 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	52.370s	1.650ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	16.120s	759.992us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.770s	24.695us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.650s	55.922us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.030s	64.074us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.060s	141.065us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.670s	23.276us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.650s	55.922us	1	1	100.00
		i2c_csr_aliasing	2.060s	141.065us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.510s	240.951us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	20.875m	41.166ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	2.547m	7.902ms	1	1	100.00
V2	host_override	i2c_host_override	1.560s	31.442us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	52.770s	63.370ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	37.890s	3.454ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.770s	277.959us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.370s	290.673us	1	1	100.00
		i2c_host_fifo_reset_rx	3.580s	512.137us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.683m	5.559ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	28.800s	1.932ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.910s	25.309us	0	1	0.00
V2	target_glitch	i2c_target_glitch	6.430s	2.238ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	4.189m	120.211ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.270s	2.863ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	27.830s	6.179ms	1	1	100.00
		i2c_target_intr_smoke	5.000s	2.916ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.910s	627.464us	1	1	100.00
		i2c_target_fifo_reset_tx	1.700s	132.394us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	7.800s	10.232ms	1	1	100.00
		i2c_target_stress_rd	27.830s	6.179ms	1	1	100.00
		i2c_target_intr_stress_wr	2.160s	165.633us	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.780s	1.374ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	12.010s	1.124ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	2.730s	411.430us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	10.740s	10.313ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.530s	2.547ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.750s	1.649ms	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	2.547m	7.902ms	1	1	100.00
		i2c_host_perf_precise	37.300s	1.451ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	28.800s	1.932ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.040s	187.459us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.110s	615.638us	1	1	100.00
		i2c_target_nack_acqfull_addr	3.060s	4.562ms	1	1	100.00
		i2c_target_nack_txstretch	2.080s	235.662us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	13.180s	435.581us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.490s	496.815us	1	1	100.00
V2	alert_test	i2c_alert_test	1.570s	43.380us	1	1	100.00
V2	intr_test	i2c_intr_test	1.530s	27.051us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.190s	268.171us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.190s	268.171us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.770s	24.695us	1	1	100.00
		i2c_csr_rw	1.650s	55.922us	1	1	100.00
		i2c_csr_aliasing	2.060s	141.065us	1	1	100.00
		i2c_same_csr_outstanding	1.940s	42.454us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.770s	24.695us	1	1	100.00
		i2c_csr_rw	1.650s	55.922us	1	1	100.00
		i2c_csr_aliasing	2.060s	141.065us	1	1	100.00
		i2c_same_csr_outstanding	1.940s	42.454us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.120s	84.021us	1	1	100.00
		i2c_sec_cm	1.880s	52.937us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.120s	84.021us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	16.220s	2.607ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	3.170s	175.807us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	12.510s	888.866us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.108656110466987245648248479368420678519392154305260404754228121575534764855456
      Line 87, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2607156406 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2607156406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.72129777971330727763714536294524769754156684449702459555981242176099281152982
      Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 888866135 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 888866135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.6296622784923035267154260434664953798886907225819862996208594194410116839160
      Line 255, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 41166380093 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @26448152
      

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.67157043785037827736024562243520174220565173572637791752356104278095805429176
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 175807097 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 175807097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.100259172027315389335518866613797373815322335586426128396134559548299313285899
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10312666878 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10312666878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.111104600976126844332116433841645176203545867137909783117049723846908332074305
      Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @  25308875 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
        --> EXP:
        ---------------------------------------------------
        Name            Type                Size  Value
        ---------------------------------------------------