KEYMGR Simulation Results

Monday May 19 2025 17:04:48 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.840s	33.407us	1	1	100.00
V1	random	keymgr_random	7.560s	334.087us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.870s	33.623us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.840s	95.134us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	6.910s	326.534us	0	1	0.00
V1	csr_aliasing	keymgr_csr_aliasing	4.200s	144.581us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.530s	189.370us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.840s	95.134us	1	1	100.00
		keymgr_csr_aliasing	4.200s	144.581us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	4.710s	108.825us	1	1	100.00
V2	sideload	keymgr_sideload	2.910s	87.536us	1	1	100.00
		keymgr_sideload_kmac	2.680s	33.945us	1	1	100.00
		keymgr_sideload_aes	3.100s	64.411us	1	1	100.00
		keymgr_sideload_otbn	3.030s	50.246us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	4.790s	197.813us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.420s	95.234us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	5.340s	188.092us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	22.350s	2.638ms	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	20.670s	1.662ms	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	3.010s	403.176us	1	1	100.00
V2	stress_all	keymgr_stress_all	15.650s	1.843ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.600s	9.913us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.850s	25.104us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.310s	781.611us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.310s	781.611us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.870s	33.623us	1	1	100.00
		keymgr_csr_rw	1.840s	95.134us	1	1	100.00
		keymgr_csr_aliasing	4.200s	144.581us	1	1	100.00
		keymgr_same_csr_outstanding	2.060s	94.765us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.870s	33.623us	1	1	100.00
		keymgr_csr_rw	1.840s	95.134us	1	1	100.00
		keymgr_csr_aliasing	4.200s	144.581us	1	1	100.00
		keymgr_same_csr_outstanding	2.060s	94.765us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	5.730s	1.032ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	5.730s	1.032ms	1	1	100.00
		keymgr_tl_intg_err	3.320s	164.022us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.840s	134.920us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.840s	134.920us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.840s	134.920us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.840s	134.920us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	7.370s	915.108us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	5.730s	1.032ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	5.730s	1.032ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	3.320s	164.022us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.840s	134.920us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	4.710s	108.825us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	7.560s	334.087us	1	1	100.00
		keymgr_csr_rw	1.840s	95.134us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	7.560s	334.087us	1	1	100.00
		keymgr_csr_rw	1.840s	95.134us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	7.560s	334.087us	1	1	100.00
		keymgr_csr_rw	1.840s	95.134us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.420s	95.234us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	20.670s	1.662ms	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	20.670s	1.662ms	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	7.560s	334.087us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	3.680s	73.346us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	5.730s	1.032ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	5.730s	1.032ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	5.730s	1.032ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	4.640s	172.198us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.420s	95.234us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	5.730s	1.032ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	5.730s	1.032ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	5.730s	1.032ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	4.640s	172.198us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	4.640s	172.198us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	5.730s	1.032ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	4.640s	172.198us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	5.730s	1.032ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	4.640s	172.198us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	4.890s	775.684us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			28	30	93.33

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.34850841075763639970701455551829906928585166577151590069904868245149667653892
      Line 346, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 775684464 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 775684464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test keymgr_csr_bit_bash has 1 failures.

    • 0.keymgr_csr_bit_bash.68901729623714793391746818207154664441653190349359968956328364741958564839946
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
        UVM_ERROR @ 326534058 ps: (keymgr_csr_assert_fpv.sv:459) [ASSERT FAILED] attest_sw_binding_5_rd_A
        UVM_INFO @ 326534058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---