KMAC/MASKED Simulation Results

Monday May 19 2025 17:04:48 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	57.950s	10.529ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.000s	104.587us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.800s	15.605us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.920s	642.206us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.820s	398.240us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.110s	379.573us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.800s	15.605us	1	1	100.00
		kmac_csr_aliasing	6.820s	398.240us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.720s	14.524us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.150s	200.545us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	18.286m	14.110ms	1	1	100.00
V2	burst_write	kmac_burst_write	9.929m	36.319ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.890s	3.991ms	1	1	100.00
		kmac_test_vectors_sha3_256	29.760s	1.941ms	1	1	100.00
		kmac_test_vectors_sha3_384	22.130s	1.497ms	1	1	100.00
		kmac_test_vectors_sha3_512	16.860s	20.258ms	1	1	100.00
		kmac_test_vectors_shake_128	3.316m	92.555ms	1	1	100.00
		kmac_test_vectors_shake_256	5.006m	63.667ms	1	1	100.00
		kmac_test_vectors_kmac	3.600s	285.444us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.660s	473.096us	1	1	100.00
V2	sideload	kmac_sideload	3.520m	17.489ms	1	1	100.00
V2	app	kmac_app	2.908m	15.137ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.739m	33.064ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.554m	3.055ms	1	1	100.00
V2	error	kmac_error	2.018m	6.635ms	1	1	100.00
V2	key_error	kmac_key_error	11.130s	8.335ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.640s	98.068us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	37.870s	5.101ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.920s	46.222us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	10.030s	10.613ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.250s	103.059us	1	1	100.00
V2	stress_all	kmac_stress_all	5.879m	34.973ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.780s	104.929us	1	1	100.00
V2	alert_test	kmac_alert_test	1.920s	21.248us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.410s	143.965us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.410s	143.965us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.000s	104.587us	1	1	100.00
		kmac_csr_rw	1.800s	15.605us	1	1	100.00
		kmac_csr_aliasing	6.820s	398.240us	1	1	100.00
		kmac_same_csr_outstanding	2.860s	408.728us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.000s	104.587us	1	1	100.00
		kmac_csr_rw	1.800s	15.605us	1	1	100.00
		kmac_csr_aliasing	6.820s	398.240us	1	1	100.00
		kmac_same_csr_outstanding	2.860s	408.728us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.040s	117.500us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.040s	117.500us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.040s	117.500us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.040s	117.500us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.850s	194.933us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	39.880s	13.773ms	1	1	100.00
		kmac_tl_intg_err	3.120s	237.899us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.120s	237.899us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.250s	103.059us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	57.950s	10.529ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.520m	17.489ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.040s	117.500us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	39.880s	13.773ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	39.880s	13.773ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	39.880s	13.773ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	57.950s	10.529ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.250s	103.059us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	39.880s	13.773ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	33.190s	6.620ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	57.950s	10.529ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.297m	2.712ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.18581571612048885044073339654726460519027804158491845546542939839175359629022
      Line 114, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2712448877 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 2712448877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---