KMAC/UNMASKED Simulation Results

Monday May 19 2025 17:04:48 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	31.870s	2.148ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.930s	164.513us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.670s	23.627us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	8.690s	4.809ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.700s	313.547us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.830s	86.938us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.670s	23.627us	1	1	100.00
		kmac_csr_aliasing	4.700s	313.547us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.610s	27.753us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.910s	40.563us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	4.616m	16.167ms	1	1	100.00
V2	burst_write	kmac_burst_write	5.384m	52.650ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	32.860s	28.480ms	1	1	100.00
		kmac_test_vectors_sha3_256	18.841m	334.933ms	1	1	100.00
		kmac_test_vectors_sha3_384	17.088m	97.574ms	1	1	100.00
		kmac_test_vectors_sha3_512	12.902m	49.576ms	1	1	100.00
		kmac_test_vectors_shake_128	2.245m	31.895ms	1	1	100.00
		kmac_test_vectors_shake_256	3.158m	41.649ms	1	1	100.00
		kmac_test_vectors_kmac	3.000s	307.106us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.490s	419.326us	1	1	100.00
V2	sideload	kmac_sideload	4.758m	62.460ms	1	1	100.00
V2	app	kmac_app	1.517m	7.941ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.386m	5.612ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.286m	74.714ms	1	1	100.00
V2	error	kmac_error	1.216m	9.267ms	1	1	100.00
V2	key_error	kmac_key_error	4.530s	467.511us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.070s	52.546us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	14.890s	1.471ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	11.640s	1.187ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	16.000s	1.049ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	8.200s	2.752ms	1	1	100.00
V2	stress_all	kmac_stress_all	1.185m	6.582ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.760s	20.156us	1	1	100.00
V2	alert_test	kmac_alert_test	1.590s	16.206us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.310s	273.415us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.310s	273.415us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.930s	164.513us	1	1	100.00
		kmac_csr_rw	1.670s	23.627us	1	1	100.00
		kmac_csr_aliasing	4.700s	313.547us	1	1	100.00
		kmac_same_csr_outstanding	2.340s	70.380us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.930s	164.513us	1	1	100.00
		kmac_csr_rw	1.670s	23.627us	1	1	100.00
		kmac_csr_aliasing	4.700s	313.547us	1	1	100.00
		kmac_same_csr_outstanding	2.340s	70.380us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.650s	302.269us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.650s	302.269us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.650s	302.269us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.650s	302.269us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.810s	342.089us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	25.810s	2.889ms	1	1	100.00
		kmac_tl_intg_err	4.340s	371.638us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.340s	371.638us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	8.200s	2.752ms	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	31.870s	2.148ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.758m	62.460ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.650s	302.269us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	25.810s	2.889ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	25.810s	2.889ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	25.810s	2.889ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	31.870s	2.148ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	8.200s	2.752ms	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	25.810s	2.889ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.880m	15.933ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	31.870s	2.148ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	10.940s	827.059us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.10740104891766008948917333283020844868372484258989883326200509535252257689997
      Line 102, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 827059064 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 827059064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---