OTBN Simulation Results

Monday May 19 2025 17:04:48 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	69.445us	1	1	100.00
V1	single_binary	otbn_single	9.000s	16.558us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	16.420us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	29.364us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	37.878us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	54.619us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	8.000s	112.834us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	29.364us	1	1	100.00
		otbn_csr_aliasing	6.000s	54.619us	1	1	100.00
V1	mem_walk	otbn_mem_walk	25.000s	1.249ms	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	15.000s	1.770ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	27.000s	297.243us	1	1	100.00
V2	multi_error	otbn_multi_err	48.000s	2.596ms	1	1	100.00
V2	back_to_back	otbn_multi	29.000s	122.139us	1	1	100.00
V2	stress_all	otbn_stress_all	32.000s	2.286ms	1	1	100.00
V2	lc_escalation	otbn_escalate	9.000s	62.781us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	35.739us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	21.000s	224.291us	1	1	100.00
V2	alert_test	otbn_alert_test	6.000s	51.981us	1	1	100.00
V2	intr_test	otbn_intr_test	6.000s	132.562us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	8.000s	90.743us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	8.000s	90.743us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	16.420us	1	1	100.00
		otbn_csr_rw	6.000s	29.364us	1	1	100.00
		otbn_csr_aliasing	6.000s	54.619us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	16.152us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	16.420us	1	1	100.00
		otbn_csr_rw	6.000s	29.364us	1	1	100.00
		otbn_csr_aliasing	6.000s	54.619us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	16.152us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	9.000s	50.522us	1	1	100.00
		otbn_dmem_err	11.000s	23.091us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	14.000s	70.178us	1	1	100.00
		otbn_controller_ispr_rdata_err	12.000s	580.299us	1	1	100.00
		otbn_mac_bignum_acc_err	10.000s	58.491us	1	1	100.00
		otbn_urnd_err	16.000s	104.276us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	17.698us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	14.000s	59.497us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	7.000s	48.493us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	1.500m	2.219ms	1	1	100.00
		otbn_tl_intg_err	11.000s	218.316us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	15.000s	87.051us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	1.500m	2.219ms	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	1.500m	2.219ms	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	69.445us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	11.000s	23.091us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	9.000s	50.522us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	11.000s	218.316us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	9.000s	62.781us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	9.000s	50.522us	1	1	100.00
		otbn_dmem_err	11.000s	23.091us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	35.739us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	17.698us	1	1	100.00
		otbn_sec_cm	1.500m	2.219ms	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	1.500m	2.219ms	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	9.000s	16.558us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	9.000s	50.522us	1	1	100.00
		otbn_dmem_err	11.000s	23.091us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	35.739us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	17.698us	1	1	100.00
		otbn_sec_cm	1.500m	2.219ms	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	1.500m	2.219ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	9.000s	62.781us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	9.000s	50.522us	1	1	100.00
		otbn_dmem_err	11.000s	23.091us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	35.739us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	17.698us	1	1	100.00
		otbn_sec_cm	1.500m	2.219ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	1.500m	2.219ms	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	9.000s	16.558us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	8.000s	203.666us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	34.674us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	27.000s	277.808us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	27.000s	277.808us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	97.096us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	1.500m	2.219ms	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	1.500m	2.219ms	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	11.000s	65.403us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	1.500m	2.219ms	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	1.500m	2.219ms	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	83.374us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	83.374us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	7.000s	27.476us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	9.000s	16.558us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	9.000s	16.558us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	9.000s	16.558us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	29.000s	122.139us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	9.000s	16.558us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	9.000s	16.558us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	8.000s	49.905us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	9.000s	16.558us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	1.500m	2.219ms	1	1	100.00
V2S		TOTAL			20	20	100.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	1.350m	420.936us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			40	41	97.56

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.104964299437515075206840026238738571840382680907432924872874173246710469262842
      Line 302, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 420935951 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 420935951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---