ROM_CTRL/32KB Simulation Results

Monday May 19 2025 17:04:48 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 4.350s 517.800us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 6.040s 171.094us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 5.010s 167.161us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.050s 385.950us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.390s 536.034us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 4.280s 218.420us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 5.010s 167.161us 1 1 100.00
rom_ctrl_csr_aliasing 4.390s 536.034us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 3.800s 370.804us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 3.870s 435.755us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.390s 139.026us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 15.090s 1.157ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 6.670s 713.488us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.820s 128.083us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 5.320s 213.242us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 5.320s 213.242us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 6.040s 171.094us 1 1 100.00
rom_ctrl_csr_rw 5.010s 167.161us 1 1 100.00
rom_ctrl_csr_aliasing 4.390s 536.034us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.110s 206.746us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 6.040s 171.094us 1 1 100.00
rom_ctrl_csr_rw 5.010s 167.161us 1 1 100.00
rom_ctrl_csr_aliasing 4.390s 536.034us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.110s 206.746us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 53.600s 7.541ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 12.670s 417.038us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.898m 990.494us 1 1 100.00
rom_ctrl_tl_intg_err 24.300s 387.069us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.898m 990.494us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.898m 990.494us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 53.600s 7.541ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 53.600s 7.541ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 53.600s 7.541ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 53.600s 7.541ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 53.600s 7.541ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.898m 990.494us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.898m 990.494us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 4.350s 517.800us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 4.350s 517.800us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 4.350s 517.800us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 24.300s 387.069us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 53.600s 7.541ms 1 1 100.00
rom_ctrl_kmac_err_chk 6.670s 713.488us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 53.600s 7.541ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 53.600s 7.541ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 53.600s 7.541ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 12.670s 417.038us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.898m 990.494us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 3.014m 24.313ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00