ROM_CTRL/64KB Simulation Results

Monday May 19 2025 17:04:48 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 6.730s 773.269us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 11.030s 308.420us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 5.690s 1.872ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.410s 387.086us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.070s 300.541us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 9.780s 4.015ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 5.690s 1.872ms 1 1 100.00
rom_ctrl_csr_aliasing 7.070s 300.541us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 5.620s 1.536ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 7.090s 299.101us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.230s 388.912us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 17.930s 585.482us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 12.250s 401.923us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.160s 1.032ms 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 7.670s 699.923us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 7.670s 699.923us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 11.030s 308.420us 1 1 100.00
rom_ctrl_csr_rw 5.690s 1.872ms 1 1 100.00
rom_ctrl_csr_aliasing 7.070s 300.541us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.530s 293.521us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 11.030s 308.420us 1 1 100.00
rom_ctrl_csr_rw 5.690s 1.872ms 1 1 100.00
rom_ctrl_csr_aliasing 7.070s 300.541us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.530s 293.521us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 2.032m 8.982ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 36.160s 6.146ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 4.992m 11.826ms 1 1 100.00
rom_ctrl_tl_intg_err 1.083m 1.579ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 4.992m 11.826ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 4.992m 11.826ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.032m 8.982ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.032m 8.982ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.032m 8.982ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.032m 8.982ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.032m 8.982ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 4.992m 11.826ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 4.992m 11.826ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 6.730s 773.269us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 6.730s 773.269us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 6.730s 773.269us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.083m 1.579ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.032m 8.982ms 1 1 100.00
rom_ctrl_kmac_err_chk 12.250s 401.923us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 2.032m 8.982ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 2.032m 8.982ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 2.032m 8.982ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 36.160s 6.146ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 4.992m 11.826ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 2.014m 19.099ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00