RV_TIMER Simulation Results

Monday May 19 2025 17:04:48 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.500s	11.266us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.530s	17.751us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.520s	43.801us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.200s	87.368us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.880s	55.391us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.050s	63.073us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.520s	43.801us	1	1	100.00
		rv_timer_csr_aliasing	1.880s	55.391us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.550s	23.917us	1	1	100.00
V2	disabled	rv_timer_disabled	2.790s	1.117ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	2.272m	224.675ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	2.272m	224.675ms	1	1	100.00
V2	stress	rv_timer_stress_all	5.130s	3.653ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.440s	207.211us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.620s	36.655us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.870s	747.383us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.870s	747.383us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.530s	17.751us	1	1	100.00
		rv_timer_csr_rw	1.520s	43.801us	1	1	100.00
		rv_timer_csr_aliasing	1.880s	55.391us	1	1	100.00
		rv_timer_same_csr_outstanding	1.620s	46.647us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.530s	17.751us	1	1	100.00
		rv_timer_csr_rw	1.520s	43.801us	1	1	100.00
		rv_timer_csr_aliasing	1.880s	55.391us	1	1	100.00
		rv_timer_same_csr_outstanding	1.620s	46.647us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.700s	129.142us	1	1	100.00
		rv_timer_tl_intg_err	1.700s	159.773us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.700s	159.773us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	22.070s	39.968ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.590s	40.301us	1	1	100.00
		rv_timer_max	1.530s	28.797us	1	1	100.00
		TOTAL			19	19	100.00