SPI_DEVICE/1R1W Simulation Results

Monday May 19 2025 17:04:48 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	3.280s	561.615us	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.250s	50.498us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.930s	78.622us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	16.340s	1.493ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.200s	220.683us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.540s	52.519us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.930s	78.622us	1	1	100.00
		spi_device_csr_aliasing	6.200s	220.683us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.710s	29.969us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.300s	269.401us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.690s	17.057us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.610s	8.119us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.630s	4.598us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.590s	42.352us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.590s	42.352us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	1.800s	155.783us	1	1	100.00
		spi_device_tpm_sts_read	1.640s	41.769us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	4.440s	402.806us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.430s	1.331ms	1	1	100.00
		spi_device_flash_all	1.533m	39.146ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	9.300s	3.254ms	1	1	100.00
		spi_device_flash_all	1.533m	39.146ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	9.300s	3.254ms	1	1	100.00
		spi_device_flash_all	1.533m	39.146ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.533m	39.146ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	6.150s	1.168ms	1	1	100.00
		spi_device_flash_all	1.533m	39.146ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	6.150s	1.168ms	1	1	100.00
		spi_device_flash_all	1.533m	39.146ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	6.150s	1.168ms	1	1	100.00
		spi_device_flash_all	1.533m	39.146ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	6.150s	1.168ms	1	1	100.00
		spi_device_flash_all	1.533m	39.146ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	6.150s	1.168ms	1	1	100.00
		spi_device_flash_all	1.533m	39.146ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	2.900s	120.449us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	6.690s	332.788us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	6.690s	332.788us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	6.690s	332.788us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	8.060s	698.778us	1	1	100.00
		spi_device_read_buffer_direct	3.420s	797.948us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	6.690s	332.788us	1	1	100.00
		spi_device_flash_all	1.533m	39.146ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.533m	39.146ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.533m	39.146ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.180s	1.253ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.180s	1.253ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	3.280s	561.615us	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.863m	66.414ms	1	1	100.00
V2	stress_all	spi_device_stress_all	50.540s	3.788ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.830s	47.582us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.660s	28.848us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.800s	1.042ms	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.800s	1.042ms	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.250s	50.498us	1	1	100.00
		spi_device_csr_rw	1.930s	78.622us	1	1	100.00
		spi_device_csr_aliasing	6.200s	220.683us	1	1	100.00
		spi_device_same_csr_outstanding	2.530s	139.331us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.250s	50.498us	1	1	100.00
		spi_device_csr_rw	1.930s	78.622us	1	1	100.00
		spi_device_csr_aliasing	6.200s	220.683us	1	1	100.00
		spi_device_same_csr_outstanding	2.530s	139.331us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.050s	687.089us	1	1	100.00
		spi_device_tl_intg_err	6.800s	299.456us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.800s	299.456us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.810s	72.613us	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.39022861948182283724768486048366132338693979586511493871342376166376679783521
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   6928894 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[22])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   6928894 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   6928894 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[918])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.102397000229193351332143995858413288006046219751156857538715013849638732262957
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   2114378 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x122c4d [100100010110001001101] vs 0x0 [0])
        UVM_ERROR @   2152378 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa21bd5 [101000100001101111010101] vs 0x0 [0])
        UVM_ERROR @   2185378 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa1d7ad [101000011101011110101101] vs 0x0 [0])
        UVM_ERROR @   2254378 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9785f8 [100101111000010111111000] vs 0x0 [0])
        UVM_ERROR @   2313378 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xac8716 [101011001000011100010110] vs 0x0 [0])