SPI_HOST Simulation Results

Monday May 19 2025 17:04:48 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.000s	621.367us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	41.775us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	26.768us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	168.171us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	37.908us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	3.000s	83.996us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	26.768us	1	1	100.00
		spi_host_csr_aliasing	3.000s	37.908us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	26.700us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	16.634us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	23.870us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	5.000s	368.407us	1	1	100.00
		spi_host_error_cmd	3.000s	114.695us	1	1	100.00
		spi_host_event	18.000s	1.164ms	1	1	100.00
V2	clock_rate	spi_host_speed	5.000s	612.780us	1	1	100.00
V2	speed	spi_host_speed	5.000s	612.780us	1	1	100.00
V2	chip_select_timing	spi_host_speed	5.000s	612.780us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	35.000s	2.471ms	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	77.701us	1	1	100.00
V2	cpol_cpha	spi_host_speed	5.000s	612.780us	1	1	100.00
V2	full_cycle	spi_host_speed	5.000s	612.780us	1	1	100.00
V2	duplex	spi_host_smoke	10.000s	621.367us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	10.000s	621.367us	1	1	100.00
V2	stress_all	spi_host_stress_all	11.000s	415.649us	1	1	100.00
V2	spien	spi_host_spien	6.000s	439.592us	1	1	100.00
V2	stall	spi_host_status_stall	33.000s	1.881ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	791.182us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	5.000s	368.407us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	17.725us	1	1	100.00
V2	intr_test	spi_host_intr_test	3.000s	28.116us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	84.127us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	84.127us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	41.775us	1	1	100.00
		spi_host_csr_rw	4.000s	26.768us	1	1	100.00
		spi_host_csr_aliasing	3.000s	37.908us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	48.392us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	41.775us	1	1	100.00
		spi_host_csr_rw	4.000s	26.768us	1	1	100.00
		spi_host_csr_aliasing	3.000s	37.908us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	48.392us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	54.647us	1	1	100.00
		spi_host_sec_cm	3.000s	78.157us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	54.647us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	4.933m	19.042ms	1	1	100.00
		TOTAL			26	26	100.00