SRAM_CTRL/MAIN Simulation Results

Monday May 19 2025 17:04:48 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	23.290s	2.835ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.470s	27.191us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.620s	203.741us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.240s	78.409us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.630s	188.236us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.430s	1.477ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.620s	203.741us	1	1	100.00
		sram_ctrl_csr_aliasing	1.630s	188.236us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.796m	7.131ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.010m	17.374ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	55.580s	3.454ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.597m	27.401ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	26.405m	357.964ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.789m	38.642ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	35.780s	30.152ms	1	1	100.00
V2	executable	sram_ctrl_executable	6.424m	30.617ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	20.340s	1.700ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.224m	5.541ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	31.440s	10.525ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	17.870s	1.490ms	1	1	100.00
		sram_ctrl_throughput_w_readback	10.180s	702.107us	1	1	100.00
V2	regwen	sram_ctrl_regwen	5.355m	11.139ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.410s	1.365ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	29.464m	108.997ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.870s	42.178us	0	1	0.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.030s	619.005us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.030s	619.005us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.470s	27.191us	1	1	100.00
		sram_ctrl_csr_rw	1.620s	203.741us	1	1	100.00
		sram_ctrl_csr_aliasing	1.630s	188.236us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.610s	48.947us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.470s	27.191us	1	1	100.00
		sram_ctrl_csr_rw	1.620s	203.741us	1	1	100.00
		sram_ctrl_csr_aliasing	1.630s	188.236us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.610s	48.947us	1	1	100.00
V2		TOTAL			16	17	94.12
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	35.170s	14.790ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.920s	7.073us	0	1	0.00
		sram_ctrl_tl_intg_err	2.560s	1.319ms	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.920s	7.073us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.560s	1.319ms	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	5.355m	11.139ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	5.355m	11.139ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.620s	203.741us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	6.424m	30.617ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	6.424m	30.617ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	6.424m	30.617ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	35.780s	30.152ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	6.210s	700.201us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	35.170s	14.790ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.320s	1.284ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	23.290s	2.835ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	23.290s	2.835ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	6.424m	30.617ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.920s	7.073us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	35.780s	30.152ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.920s	7.073us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.920s	7.073us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	23.290s	2.835ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.920s	7.073us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	37.600s	7.980ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.109794720476992614154474915067182996873817480389541647974530237954301475412618
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7072738 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7072738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '((pend_req[*].pend == *'b0) || $test$plusargs("disable_assert_final_checks"))' has 1 failures:

  • Test sram_ctrl_alert_test has 1 failures.

    • 0.sram_ctrl_alert_test.79007131788411136806819951461232670205729543119668729601501415278514511201005
      Line 129, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_alert_test/latest/run.log

            Offending '((pend_req[59].pend == 1'b0) || $test$plusargs("disable_assert_final_checks"))'
        UVM_ERROR @  42177753 ps: (tlul_assert.sv:301) [ASSERT FAILED] noOutstandingReqsAtEndOfSim_A
        UVM_INFO @  42177753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---