SRAM_CTRL/RET Simulation Results

Monday May 19 2025 17:04:48 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	4.590s	1.706ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.830s	40.419us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.650s	14.362us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.520s	468.604us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.580s	35.093us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.060s	243.975us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.650s	14.362us	1	1	100.00
		sram_ctrl_csr_aliasing	1.580s	35.093us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.900s	449.645us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.090s	670.735us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.325m	82.157ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.495m	9.985ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	49.510s	13.204ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	4.451m	2.522ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	7.280s	6.396ms	1	1	100.00
V2	executable	sram_ctrl_executable	12.863m	19.366ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	4.180s	564.197us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.380m	14.925ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.360s	147.368us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	3.290s	51.128us	1	1	100.00
		sram_ctrl_throughput_w_readback	36.310s	717.534us	1	1	100.00
V2	regwen	sram_ctrl_regwen	17.230s	381.093us	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.620s	29.721us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	22.261m	7.578ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.710s	19.416us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.080s	35.250us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.080s	35.250us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.830s	40.419us	1	1	100.00
		sram_ctrl_csr_rw	1.650s	14.362us	1	1	100.00
		sram_ctrl_csr_aliasing	1.580s	35.093us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.520s	60.163us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.830s	40.419us	1	1	100.00
		sram_ctrl_csr_rw	1.650s	14.362us	1	1	100.00
		sram_ctrl_csr_aliasing	1.580s	35.093us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.520s	60.163us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.680s	816.010us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.470s	3.340us	0	1	0.00
		sram_ctrl_tl_intg_err	2.890s	611.324us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.470s	3.340us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.890s	611.324us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	17.230s	381.093us	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	17.230s	381.093us	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.650s	14.362us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	12.863m	19.366ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	12.863m	19.366ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	12.863m	19.366ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	7.280s	6.396ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.690s	76.308us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.680s	816.010us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.670s	141.912us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	4.590s	1.706ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	4.590s	1.706ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	12.863m	19.366ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.470s	3.340us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	7.280s	6.396ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.470s	3.340us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.470s	3.340us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	4.590s	1.706ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.470s	3.340us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.228m	3.211ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(depth_o <= *'(Depth))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.90749410149303004730914292743831976476567947245742738635107206969951115458412
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   3339863 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   3339863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---