UART Simulation Results

Monday May 19 2025 17:04:48 UTC

GitHub Revision: b21d4d7

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	6.290s	6.108ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.490s	38.514us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.480s	30.560us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.010s	96.105us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.550s	181.021us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.590s	216.829us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.480s	30.560us	1	1	100.00
		uart_csr_aliasing	1.550s	181.021us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	37.860s	122.204ms	1	1	100.00
V2	parity	uart_smoke	6.290s	6.108ms	1	1	100.00
		uart_tx_rx	37.860s	122.204ms	1	1	100.00
V2	parity_error	uart_intr	43.850s	25.970ms	1	1	100.00
		uart_rx_parity_err	58.390s	109.320ms	1	1	100.00
V2	watermark	uart_tx_rx	37.860s	122.204ms	1	1	100.00
		uart_intr	43.850s	25.970ms	1	1	100.00
V2	fifo_full	uart_fifo_full	17.600s	32.237ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	32.460s	187.117ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	1.191m	130.743ms	1	1	100.00
V2	rx_frame_err	uart_intr	43.850s	25.970ms	1	1	100.00
V2	rx_break_err	uart_intr	43.850s	25.970ms	1	1	100.00
V2	rx_timeout	uart_intr	43.850s	25.970ms	1	1	100.00
V2	perf	uart_perf	1.372m	19.907ms	1	1	100.00
V2	sys_loopback	uart_loopback	1.570s	76.715us	1	1	100.00
V2	line_loopback	uart_loopback	1.570s	76.715us	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	30.040s	181.824ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.100s	3.989ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	3.700s	1.629ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	30.210s	5.058ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.628m	52.581ms	1	1	100.00
V2	stress_all	uart_stress_all	48.520s	32.066ms	1	1	100.00
V2	alert_test	uart_alert_test	1.540s	12.585us	1	1	100.00
V2	intr_test	uart_intr_test	1.490s	13.052us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.240s	72.317us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.240s	72.317us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.490s	38.514us	1	1	100.00
		uart_csr_rw	1.480s	30.560us	1	1	100.00
		uart_csr_aliasing	1.550s	181.021us	1	1	100.00
		uart_same_csr_outstanding	1.660s	28.456us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.490s	38.514us	1	1	100.00
		uart_csr_rw	1.480s	30.560us	1	1	100.00
		uart_csr_aliasing	1.550s	181.021us	1	1	100.00
		uart_same_csr_outstanding	1.660s	28.456us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.650s	36.436us	1	1	100.00
		uart_tl_intg_err	1.790s	67.093us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.790s	67.093us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	36.100s	17.107ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00