CHIP Simulation Results

Monday May 19 2025 17:04:48 UTC

GitHub Revision: `b21d4d7`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.440m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.440m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	2.111m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	2.003m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.814m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.838m	4.704ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.838m	4.704ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.838m	4.704ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	38.390s	10.340us	0	1	0.00
		chip_sw_example_manufacturer	2.554m		0	1	0.00
		chip_sw_example_concurrency	4.463m	5.480ms	1	1	100.00
		chip_sw_uart_smoketest_signed	14.908s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	10.440s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	10.690s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	10.690s		0	1	0.00
V1	xbar_smoke	xbar_smoke	18.880s	59.140us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	2.344m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	12.447m	9.795ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	5.008m	4.599ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	1.639m		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	1.317m		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.782m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	1.819m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.440s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.440s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.868m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.256m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.626m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.626m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.540m	3.777ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.831m	4.542ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.581m	13.563ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	10.766s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.356s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	15.516m	26.337ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.538m	4.153ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	18.775m	18.026ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	18.775m	18.026ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	37.703s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.271m	5.498ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.271m	5.498ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.301m	18.023ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.385m	4.574ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	4.864m	4.075ms	1	1	100.00
		chip_sw_aes_idle	3.550m	4.347ms	1	1	100.00
		chip_sw_hmac_enc_idle	5.072m	5.115ms	1	1	100.00
		chip_sw_kmac_idle	3.984m	5.557ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	11.962m	12.016ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	13.271m	12.017ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	13.199m	11.441ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	10.910m	12.022ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	13.802s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.784s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	22.329s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.037s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.188s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.209s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.379s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	13.802s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.784s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	22.329s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.037s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.188s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.209s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.379s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	18.996s		0	1	0.00
		chip_sw_aes_enc_jitter_en	48.980s	10.400us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	48.310s	10.240us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	47.770s	10.100us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	45.650s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.125s		0	1	0.00
		chip_sw_clkmgr_jitter	3.656m	5.619ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.517m	4.559ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	13.056s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	48.790s	10.120us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	1.024m	10.140us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	47.640s	10.240us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	52.260s	10.320us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	47.780s	10.400us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	13.230s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	10.906s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.057s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.502s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	20.536m	15.974ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.961m	10.842ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	5.271m	5.498ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	20.318s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.961m	10.842ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	15.232s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	12.076s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	38.207s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	16.410s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	28.871s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	20.536m	15.974ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.581m	13.563ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	21.005m	20.021ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.042m	8.929ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	10.137m	10.153ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.794m	3.661ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	20.536m	15.974ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	11.204s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	12.366s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	20.536m	15.974ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	10.616s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	10.137m	10.153ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	13.013s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	13.254s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	12.471s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	12.942s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	12.416s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	16.239s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	12.366s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	15.760s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	13.217s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	15.760s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	15.760s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	15.760s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.211m	8.602ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	13.656s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	11.770s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	18.881s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	12.402s		0	1	0.00
		chip_sw_lc_ctrl_transition	15.760s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.834m	10.115ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.360m	11.368ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.286s		0	1	0.00
		chip_prim_tl_access	10.449m	15.114ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	13.802s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.784s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	22.329s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.037s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.188s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.209s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.379s		0	1	0.00
		chip_rv_dm_lc_disabled	15.516m	26.337ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.179m	3.523ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	48.980s	10.400us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.231m	4.512ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.550m	4.347ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.896m	3.989ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	48.310s	10.240us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.072m	5.115ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.988m	3.698ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.506m	5.730ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	45.650s	10.200us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.834m	10.115ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	15.760s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	40.840s	10.380us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.540m	5.041ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.984m	5.557ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.867s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.867s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.162s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.351m	4.102ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	15.228s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.834m	10.115ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	47.770s	10.100us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	15.839s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	18.996s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	4.864m	4.075ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	4.864m	4.075ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	4.864m	4.075ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	6.813m	4.445ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.360m	11.368ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.360m	11.368ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.932m	7.879ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.125s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.286s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	20.536m	15.974ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.626m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	15.760s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	6.813m	4.445ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.834m	10.115ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	6.932m	7.879ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.155m	5.024ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	6.813m	4.445ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.834m	10.115ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	6.932m	7.879ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.155m	5.024ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	15.760s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	10.924s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	13.217s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	13.656s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	11.770s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	18.881s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	12.402s		0	1	0.00
		chip_sw_lc_ctrl_transition	15.760s		0	1	0.00
		chip_prim_tl_access	10.449m	15.114ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	10.449m	15.114ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	15.920s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	12.715s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	10.906s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	18.996s		0	1	0.00
		chip_sw_aes_enc_jitter_en	48.980s	10.400us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	48.310s	10.240us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	47.770s	10.100us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	45.650s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.125s		0	1	0.00
		chip_sw_clkmgr_jitter	3.656m	5.619ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	8.202m	9.977ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	8.202m	9.977ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.532m	3.243ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.947m	3.842ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.194m	3.947ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.758m	5.014ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.104m	5.683ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.505m	5.803ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.155m	5.024ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	21.005m	20.021ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	21.005m	20.021ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.668m	4.146ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.100m	3.440ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.519m	5.095ms	1	1	100.00
		chip_sw_csrng_smoketest	3.429m	3.495ms	1	1	100.00
		chip_sw_gpio_smoketest	3.328m	4.508ms	1	1	100.00
		chip_sw_hmac_smoketest	4.509m	5.969ms	1	1	100.00
		chip_sw_kmac_smoketest	3.215m	3.601ms	1	1	100.00
		chip_sw_otbn_smoketest	4.545m	5.566ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.420m	4.500ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.717m	5.861ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.078m	6.287ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.425m	4.024ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.693m	5.277ms	1	1	100.00
		chip_sw_uart_smoketest	3.726m	5.130ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	20.316s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	14.908s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.344m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.295s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.309m	5.701ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.256m	4.463ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.318m	6.301ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.034m	5.860ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	21.548s		0	1	0.00
		chip_rv_dm_lc_disabled	15.516m	26.337ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	11.398s		0	1	0.00
		chip_sw_lc_walkthrough_prod	41.148s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	14.590s		0	1	0.00
		chip_sw_lc_walkthrough_rma	12.371s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	21.548s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	23.003s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	24.892s		0	1	0.00
		rom_volatile_raw_unlock	10.913s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	15.357s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.249m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.488m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.703m	5.330ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.703m	5.330ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	10.690s		0	1	0.00
		chip_same_csr_outstanding	9.680s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	10.690s		0	1	0.00
		chip_same_csr_outstanding	9.680s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	2.287m	408.022us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.300s	10.985us	1	1	100.00
		xbar_smoke_large_delays	4.251m	2.244ms	1	1	100.00
		xbar_smoke_slow_rsp	5.054m	1.957ms	1	1	100.00
		xbar_random_zero_delays	16.200s	14.970us	1	1	100.00
		xbar_random_large_delays	13.659m	7.022ms	1	1	100.00
		xbar_random_slow_rsp	32.542m	12.995ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	25.790s	18.232us	1	1	100.00
		xbar_error_and_unmapped_addr	35.090s	23.676us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	13.770s	32.210us	1	1	100.00
		xbar_error_and_unmapped_addr	35.090s	23.676us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	40.540s	98.290us	1	1	100.00
		xbar_access_same_device_slow_rsp	41.942m	16.910ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.843m	340.207us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	6.100m	1.117ms	1	1	100.00
		xbar_stress_all_with_error	7.110m	455.351us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	1.826m	237.046us	1	1	100.00
		xbar_stress_all_with_reset_error	8.410m	320.999us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	12.345s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.975s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	13.025s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.030s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	10.623s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	13.610s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	10.755s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	10.797s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.482s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.021s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	10.766s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.308s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	13.008s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.975s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.268s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	12.333s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	12.456s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.828s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	12.047s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	11.425s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	11.247s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	11.452s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	12.431s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	12.684s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.538s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.308s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	13.054s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	11.852s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.534s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.562s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	13.059s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	11.483s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	11.652s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.223s		0	1	0.00
		rom_e2e_asm_init_dev	11.654s		0	1	0.00
		rom_e2e_asm_init_prod	12.092s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.468s		0	1	0.00
		rom_e2e_asm_init_rma	13.389s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.798s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	12.214s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.656s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.738s		0	1	0.00
V2		TOTAL			66	205	32.20
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.273m	5.829ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.127m	4.926ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.209s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.773s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.340s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	13.536s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	20.536m	15.974ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	13.672s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	17.207m	13.923ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	10.658s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.228s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.209s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.773s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.340s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.007s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.923s		0	1	0.00
		rom_e2e_jtag_inject_rma	10.988s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.123m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	19.749m	15.691ms	1	1	100.00
		chip_plic_all_irqs_0	8.292m	7.579ms	1	1	100.00
		chip_plic_all_irqs_10	9.556m	8.401ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.310m	4.500ms	1	1	100.00
		chip_sw_dma_abort	4.675m	5.879ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.894s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.562s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.334s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.335s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.260s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.338s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.503s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.003s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.655s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.284s		0	1	0.00
		chip_sw_mbx_smoketest	4.221m	5.538ms	1	1	100.00
		TOTAL			77	247	31.17

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.58319518858751743521321695437774691928390008802804087178996560956379396919425
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (5f6b79)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 141.699s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.70119851794294569012282869711975750994020789626227271219041144769958587244928
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (e4e3eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 145.308s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.64542299383309246904833313007666289743056321228539780655370209418920505088310
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b7d3f1)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 161.299s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.95242280577093523201680418668188467368605948041873723493442075445875685991099
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (bec259)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 124.257s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.39178484152451564028987791107597066163710938782999168304765583791412313586684
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (d0a596)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 135.312s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.10385260909026033318119558218842394052517360266807290030028474473313311438934
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.99240293421131906201798768509157220957743163851174945151486692942724682041711
    Line 424, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.48861474259039001295944996310549688784918413869805311686601848696787309435476
    Line 431, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.55089146286070287307066921283937914840756075989092250831508934828646418976436
    Line 409, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.30548951539990772226795178422536707683509799064688815188670142703853597726283
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.12794963689390836797197688092404296294244881118552432733691687155246178976624
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.37514369472267913307578797394954439745252418224739311494374544556573840487565
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.27316621371530970862266021774698879232260800105645405543341859473737723898628
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.70963399886487129602769218146662739823872387644485330066619800740352598855284
Line 467, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20020.888561 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20020.888561 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.49113367339476543338557283818685108537419766427115060555220535100482480283395
Line 480, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18025.553625 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18025.553625 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.92661561531285134702996882925017666404872479665117742066231341642057918276097
Line 460, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18023.495871 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18023.495871 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.68231957960190950879879199065197120198114007033014336098168357334652609049938
Line 441, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12015.514071 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12015.514071 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.95651692967529581082094488990091063474143011244337280104419500554919324262724
Line 448, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12016.525148 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12016.525148 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.48611995763412217533478748727099535684136488697952702771927139154642299457128
Line 441, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12022.223367 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12022.223367 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.21496143738474243580838753516676779853895029576884256503742932933746856728183
Line 484, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 10114.792344 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (112776790741381844177480223639232515558291179834794694579495143685699612083833 [0xf95566caba2af10d1c7620451aad89a4288e73923ceb7b6494f8d1b5a0ea8679] vs 3224230549290781786800505466344887988421773132787303878693329116027206880524 [0x720d98dd8bd2b98ef0b3f428d32ec4d2dfaa1305586eb44975f9407e501cd0c])
  UVM_INFO @ 10114.792344 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.71523924708920744097587309424370298852652707299912625088499851910037149997025
Line 481, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 8601.876630 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (23180519175199008193557469805585738346106117003284421116697010247836660721828 [0x333fb57b01fc79ef95a76ea9f1afd08613eb3f0f86c4ec3833b1ee71eca4e8a4] vs 48154860477528726270574943035715078694402980509070032846235288633386759437673 [0x6a76af66affc2dc1344c12869fdc2226a05f1249468fa8d1a7db42de65a93d69])
  UVM_INFO @ 8601.876630 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.89523876921065878594228360758535950505823905187630484368726538281993776135635
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3777.177150 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hf0e81fd6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3  a_opcode: 'h1  a_user: 'h248c6  d_param: 'h0  d_source: 'h3  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3777.177150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.8281142778749639540201333829020684680818782960581498289223973206085532667777
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4542.286809 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h45e386f0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h26  a_opcode: 'h1  a_user: 'h248f7  d_param: 'h0  d_source: 'h26  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4542.286809 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.109880072551819480626575885121636676628007299018737773337930719939976380783261
    Line 614, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.103827738659635697715073101849539501669236732420935857372948836884263046107031
    Line 541, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4598.505778 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4598.505778 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.98151886135650950320697711868828515895506822092043372810481749691289966950227
    Line 696, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 10152.908092 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 10152.908092 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.59305629034245528804382535254369606944310764038443912659299686683788006263547
    Line 497, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 3243.364520 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3243.364520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.52690357696629586999343507039139917352423016119259456305245237979177164011706
    Line 476, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 3842.251760 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 3842.251760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.95995445569335644196732021001671514881734301816080373347476665726269634661253
    Line 473, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 5498.118494 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 5498.118494 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.43199074199809731072559897312974645880559899600682439404481794142618978518890
    Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5014.278392 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5014.278392 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.111773551127565804120984852809917027119540546213696684364770048159619793310971
    Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@35826) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.21109587127819477113951412996919796300490630335514254873650872500061811294943
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 5330.207548 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@35826) { a_addr: 'h2210  a_data: 'hfb2d7ff  a_mask: 'h0  a_size: 'h2  a_param: 'h0  a_source: 'h61  a_opcode: 'h4  a_user: 'h2635e  d_param: 'h0  d_source: 'h61  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5330.207548 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.39569699060677265727807025085959196470616940601641829303645660345084133435850
    Line 401, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 13562.831336 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 13562.831336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.100517086277581567540249958734533014112668488181065475434803680855739524671937
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.92561207366095614335701833959050355893038746748708822024853434139357849446239
    Line 428, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5879.079720 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5879.079720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```