DMA Simulation Results

Tuesday May 20 2025 17:03:23 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	8.000s	1.223ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	8.000s	1.444ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	8.000s	339.460us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	5.000s	87.383us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	88.496us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	17.000s	2.363ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	7.000s	322.031us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	21.277us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	88.496us	1	1	100.00
		dma_csr_aliasing	7.000s	322.031us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	33.000s	4.994ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	3.433m	18.306ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	21.367m	305.953ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	2.750m	14.625ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	3.433m	18.306ms	1	1	100.00
V2	dma_abort	dma_abort	15.000s	3.453ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	2.617m	34.172ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	16.071us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	6.000s	567.215us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	6.000s	567.215us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	5.000s	87.383us	1	1	100.00
		dma_csr_rw	4.000s	88.496us	1	1	100.00
		dma_csr_aliasing	7.000s	322.031us	1	1	100.00
		dma_same_csr_outstanding	5.000s	117.110us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	5.000s	87.383us	1	1	100.00
		dma_csr_rw	4.000s	88.496us	1	1	100.00
		dma_csr_aliasing	7.000s	322.031us	1	1	100.00
		dma_same_csr_outstanding	5.000s	117.110us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	20.000s	273.241us	1	1	100.00
		dma_generic_stress	2.750m	14.625ms	1	1	100.00
		dma_handshake_stress	3.433m	18.306ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	6.000s	567.800us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.150m	6.313ms	1	1	100.00
		dma_longer_transfer	17.000s	1.705ms	1	1	100.00
		TOTAL			21	21	100.00