EDN Simulation Results

Tuesday May 20 2025 17:03:23 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.790s 38.911us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.810s 16.829us 1 1 100.00
V1 csr_rw edn_csr_rw 1.720s 13.514us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.730s 58.890us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.930s 28.984us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.950s 22.760us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.720s 13.514us 1 1 100.00
edn_csr_aliasing 1.930s 28.984us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 3.970s 247.747us 1 1 100.00
V2 csrng_commands edn_genbits 3.970s 247.747us 1 1 100.00
V2 genbits edn_genbits 3.970s 247.747us 1 1 100.00
V2 interrupts edn_intr 1.810s 21.037us 1 1 100.00
V2 alerts edn_alert 1.860s 75.183us 1 1 100.00
V2 errs edn_err 1.810s 35.665us 1 1 100.00
V2 disable edn_disable 1.730s 13.120us 1 1 100.00
edn_disable_auto_req_mode 1.810s 198.072us 1 1 100.00
V2 stress_all edn_stress_all 2.920s 229.047us 1 1 100.00
V2 intr_test edn_intr_test 1.800s 21.422us 1 1 100.00
V2 alert_test edn_alert_test 1.510s 30.904us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.150s 78.172us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.150s 78.172us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.810s 16.829us 1 1 100.00
edn_csr_rw 1.720s 13.514us 1 1 100.00
edn_csr_aliasing 1.930s 28.984us 1 1 100.00
edn_same_csr_outstanding 1.810s 39.046us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.810s 16.829us 1 1 100.00
edn_csr_rw 1.720s 13.514us 1 1 100.00
edn_csr_aliasing 1.930s 28.984us 1 1 100.00
edn_same_csr_outstanding 1.810s 39.046us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 4.500s 1.090ms 1 1 100.00
edn_tl_intg_err 2.710s 278.992us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.690s 21.143us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.860s 75.183us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 4.500s 1.090ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 4.500s 1.090ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 4.500s 1.090ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 4.500s 1.090ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.860s 75.183us 1 1 100.00
edn_sec_cm 4.500s 1.090ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.860s 75.183us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.710s 278.992us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets