HMAC Simulation Results

Tuesday May 20 2025 17:03:23 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 7.550s 2.435ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.850s 278.964us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.740s 16.941us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.540s 116.731us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.200s 631.443us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.360s 34.876us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.740s 16.941us 1 1 100.00
hmac_csr_aliasing 3.200s 631.443us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 44.710s 2.321ms 1 1 100.00
V2 back_pressure hmac_back_pressure 47.460s 2.219ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.506m 6.645ms 1 1 100.00
hmac_test_sha384_vectors 19.170s 224.660us 1 1 100.00
hmac_test_sha512_vectors 20.420s 502.356us 1 1 100.00
hmac_test_hmac256_vectors 8.370s 1.201ms 1 1 100.00
hmac_test_hmac384_vectors 8.400s 277.434us 1 1 100.00
hmac_test_hmac512_vectors 11.790s 383.964us 1 1 100.00
V2 burst_wr hmac_burst_wr 16.520s 1.306ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 7.124m 3.888ms 1 1 100.00
V2 error hmac_error 46.160s 17.771ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.210m 5.780ms 1 1 100.00
V2 save_and_restore hmac_smoke 7.550s 2.435ms 1 1 100.00
hmac_long_msg 44.710s 2.321ms 1 1 100.00
hmac_back_pressure 47.460s 2.219ms 1 1 100.00
hmac_datapath_stress 7.124m 3.888ms 1 1 100.00
hmac_burst_wr 16.520s 1.306ms 1 1 100.00
hmac_stress_all 3.795m 27.247ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 7.550s 2.435ms 1 1 100.00
hmac_long_msg 44.710s 2.321ms 1 1 100.00
hmac_back_pressure 47.460s 2.219ms 1 1 100.00
hmac_datapath_stress 7.124m 3.888ms 1 1 100.00
hmac_wipe_secret 1.210m 5.780ms 1 1 100.00
hmac_test_sha256_vectors 3.506m 6.645ms 1 1 100.00
hmac_test_sha384_vectors 19.170s 224.660us 1 1 100.00
hmac_test_sha512_vectors 20.420s 502.356us 1 1 100.00
hmac_test_hmac256_vectors 8.370s 1.201ms 1 1 100.00
hmac_test_hmac384_vectors 8.400s 277.434us 1 1 100.00
hmac_test_hmac512_vectors 11.790s 383.964us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 7.550s 2.435ms 1 1 100.00
hmac_long_msg 44.710s 2.321ms 1 1 100.00
hmac_back_pressure 47.460s 2.219ms 1 1 100.00
hmac_datapath_stress 7.124m 3.888ms 1 1 100.00
hmac_burst_wr 16.520s 1.306ms 1 1 100.00
hmac_error 46.160s 17.771ms 1 1 100.00
hmac_wipe_secret 1.210m 5.780ms 1 1 100.00
hmac_test_sha256_vectors 3.506m 6.645ms 1 1 100.00
hmac_test_sha384_vectors 19.170s 224.660us 1 1 100.00
hmac_test_sha512_vectors 20.420s 502.356us 1 1 100.00
hmac_test_hmac256_vectors 8.370s 1.201ms 1 1 100.00
hmac_test_hmac384_vectors 8.400s 277.434us 1 1 100.00
hmac_test_hmac512_vectors 11.790s 383.964us 1 1 100.00
hmac_stress_all 3.795m 27.247ms 1 1 100.00
V2 stress_all hmac_stress_all 3.795m 27.247ms 1 1 100.00
V2 alert_test hmac_alert_test 1.640s 121.258us 1 1 100.00
V2 intr_test hmac_intr_test 1.540s 12.315us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.130s 255.028us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.130s 255.028us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.850s 278.964us 1 1 100.00
hmac_csr_rw 1.740s 16.941us 1 1 100.00
hmac_csr_aliasing 3.200s 631.443us 1 1 100.00
hmac_same_csr_outstanding 3.290s 145.094us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.850s 278.964us 1 1 100.00
hmac_csr_rw 1.740s 16.941us 1 1 100.00
hmac_csr_aliasing 3.200s 631.443us 1 1 100.00
hmac_same_csr_outstanding 3.290s 145.094us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.600s 49.485us 1 1 100.00
hmac_tl_intg_err 3.920s 997.245us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.920s 997.245us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 7.550s 2.435ms 1 1 100.00
V3 stress_reset hmac_stress_reset 3.340s 1.218ms 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 37.550s 12.393ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.860s 123.511us 1 1 100.00
TOTAL 28 28 100.00