I2C Simulation Results

Tuesday May 20 2025 17:03:23 UTC

GitHub Revision: `0463149`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	19.520s	6.595ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	9.540s	1.147ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.630s	63.506us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.700s	58.274us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.420s	1.398ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.640s	236.307us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.120s	63.106us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.700s	58.274us	1	1	100.00
		i2c_csr_aliasing	2.640s	236.307us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	4.230s	1.187ms	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	10.283m	49.771ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	46.900s	7.008ms	1	1	100.00
V2	host_override	i2c_host_override	1.560s	15.221us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	55.590s	14.155ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.149m	6.671ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.900s	170.051us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.240s	436.125us	1	1	100.00
		i2c_host_fifo_reset_rx	3.610s	157.570us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	43.110s	2.761ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	7.310s	559.716us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.880s	67.469us	0	1	0.00
V2	target_glitch	i2c_target_glitch	9.700s	9.673ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	36.890s	42.561ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.280s	539.221us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	16.540s	4.071ms	1	1	100.00
		i2c_target_intr_smoke	5.160s	1.138ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.880s	525.470us	1	1	100.00
		i2c_target_fifo_reset_tx	1.840s	502.457us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.774m	39.508ms	1	1	100.00
		i2c_target_stress_rd	16.540s	4.071ms	1	1	100.00
		i2c_target_intr_stress_wr	2.285m	14.782ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.940s	1.332ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	4.120s	999.933us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.090s	3.240ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	3.160s	13.046ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.580s	381.723us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.960s	1.250ms	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	46.900s	7.008ms	1	1	100.00
		i2c_host_perf_precise	3.000s	62.992us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	7.310s	559.716us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.800s	288.704us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.850s	4.018ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.670s	831.555us	1	1	100.00
		i2c_target_nack_txstretch	2.070s	313.385us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	13.440s	1.425ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.330s	830.468us	1	1	100.00
V2	alert_test	i2c_alert_test	1.470s	41.098us	1	1	100.00
V2	intr_test	i2c_intr_test	1.630s	19.242us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.990s	113.465us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.990s	113.465us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.630s	63.506us	1	1	100.00
		i2c_csr_rw	1.700s	58.274us	1	1	100.00
		i2c_csr_aliasing	2.640s	236.307us	1	1	100.00
		i2c_same_csr_outstanding	2.200s	131.459us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.630s	63.506us	1	1	100.00
		i2c_csr_rw	1.700s	58.274us	1	1	100.00
		i2c_csr_aliasing	2.640s	236.307us	1	1	100.00
		i2c_same_csr_outstanding	2.200s	131.459us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	2.080s	266.395us	1	1	100.00
		i2c_sec_cm	1.740s	68.343us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.080s	266.395us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	10.120s	284.474us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.960s	113.875us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	24.080s	957.911us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.73996359515009350612352410191469203152979259847402059077097566177072454755504
    Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 284473539 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 284473539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.98721050996020051413921515966071365231185636454708580333194361804805605471552
    Line 121, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 957910670 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 957910670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.19688908885805808868060577380005877420627814887780489933034264310832036435411
Line 192, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 49770676479 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @6782238

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.51269935012290667267092422783817802203142562010391595054534625645516649330747
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 113875472 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 113875472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.68459740291066478052779817378300673631933731455565460288756059744681766884229
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 13045502582 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 13045502582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 0.i2c_host_mode_toggle.81842007227590824471847326829662045148956069768201983654412537661799424873431
    Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
```
  UVM_ERROR @  67469451 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:
- Test i2c_target_nack_txstretch has 1 failures.
  - 0.i2c_target_nack_txstretch.23668625419294601277345115655950275991709922721893218498388692558297220133200
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 313385176 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 313385176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```