KEYMGR Simulation Results

Tuesday May 20 2025 17:03:23 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	4.670s	468.250us	1	1	100.00
V1	random	keymgr_random	7.430s	243.966us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.060s	37.298us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.920s	43.069us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	10.520s	901.875us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	4.000s	280.567us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.660s	338.673us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.920s	43.069us	1	1	100.00
		keymgr_csr_aliasing	4.000s	280.567us	0	1	0.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	7.230s	391.215us	1	1	100.00
V2	sideload	keymgr_sideload	4.790s	145.238us	1	1	100.00
		keymgr_sideload_kmac	2.520s	56.073us	1	1	100.00
		keymgr_sideload_aes	3.790s	280.292us	1	1	100.00
		keymgr_sideload_otbn	2.760s	38.481us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.500s	364.989us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.660s	116.616us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	4.840s	309.996us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.880s	107.825us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	4.780s	251.891us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.550s	758.261us	1	1	100.00
V2	stress_all	keymgr_stress_all	5.010s	133.161us	1	1	100.00
V2	intr_test	keymgr_intr_test	1.890s	19.744us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.510s	14.946us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.380s	92.682us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.380s	92.682us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.060s	37.298us	1	1	100.00
		keymgr_csr_rw	1.920s	43.069us	1	1	100.00
		keymgr_csr_aliasing	4.000s	280.567us	0	1	0.00
		keymgr_same_csr_outstanding	2.700s	82.769us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.060s	37.298us	1	1	100.00
		keymgr_csr_rw	1.920s	43.069us	1	1	100.00
		keymgr_csr_aliasing	4.000s	280.567us	0	1	0.00
		keymgr_same_csr_outstanding	2.700s	82.769us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	4.720s	509.627us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	4.720s	509.627us	1	1	100.00
		keymgr_tl_intg_err	4.190s	323.179us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.050s	393.281us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.050s	393.281us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.050s	393.281us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.050s	393.281us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	4.140s	191.269us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	4.720s	509.627us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	4.720s	509.627us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	4.190s	323.179us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.050s	393.281us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	7.230s	391.215us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	7.430s	243.966us	1	1	100.00
		keymgr_csr_rw	1.920s	43.069us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	7.430s	243.966us	1	1	100.00
		keymgr_csr_rw	1.920s	43.069us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	7.430s	243.966us	1	1	100.00
		keymgr_csr_rw	1.920s	43.069us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.660s	116.616us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	4.780s	251.891us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	4.780s	251.891us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	7.430s	243.966us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.850s	145.728us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	4.720s	509.627us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	4.720s	509.627us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	4.720s	509.627us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	4.560s	197.213us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.660s	116.616us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	4.720s	509.627us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	4.720s	509.627us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	4.720s	509.627us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	4.560s	197.213us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	4.560s	197.213us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	4.720s	509.627us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	4.560s	197.213us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	4.720s	509.627us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	4.560s	197.213us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	14.890s	1.163ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	30	96.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test keymgr_csr_aliasing has 1 failures.

    • 0.keymgr_csr_aliasing.57557751569023127727429103137626599442324604201775962809291710100926412606130
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
        UVM_ERROR @ 280567054 ps: (keymgr_csr_assert_fpv.sv:464) [ASSERT FAILED] attest_sw_binding_6_rd_A
        UVM_INFO @ 280567054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---