| V1 |
smoke |
keymgr_dpe_smoke |
11.940s |
485.080us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
1.580s |
17.483us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
1.570s |
38.685us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
6.200s |
695.484us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
7.380s |
886.485us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
1.980s |
310.212us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
1.570s |
38.685us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
7.380s |
886.485us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
1.490s |
67.107us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
2.020s |
10.132us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
2.790s |
1.381ms |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
2.790s |
1.381ms |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
1.580s |
17.483us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.570s |
38.685us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
7.380s |
886.485us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.040s |
41.381us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
1.580s |
17.483us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.570s |
38.685us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
7.380s |
886.485us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.040s |
41.381us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
8.580s |
1.984ms |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
4.460s |
383.592us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
2.020s |
195.475us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
2.020s |
195.475us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
2.020s |
195.475us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
2.020s |
195.475us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
3.070s |
532.059us |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
8.580s |
1.984ms |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
8.580s |
1.984ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |