KMAC/MASKED Simulation Results

Tuesday May 20 2025 17:03:23 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	55.830s	7.403ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.750s	19.014us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.720s	23.195us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.160s	608.158us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.010s	401.549us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.590s	86.957us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.720s	23.195us	1	1	100.00
		kmac_csr_aliasing	7.010s	401.549us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.600s	41.774us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.890s	18.475us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	28.981m	79.236ms	1	1	100.00
V2	burst_write	kmac_burst_write	18.841m	67.826ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	30.882m	249.749ms	1	1	100.00
		kmac_test_vectors_sha3_256	34.520s	1.120ms	1	1	100.00
		kmac_test_vectors_sha3_384	22.649m	91.930ms	1	1	100.00
		kmac_test_vectors_sha3_512	18.991m	170.199ms	1	1	100.00
		kmac_test_vectors_shake_128	2.573m	7.902ms	1	1	100.00
		kmac_test_vectors_shake_256	1.862m	7.688ms	1	1	100.00
		kmac_test_vectors_kmac	3.350s	59.084us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.640s	96.643us	1	1	100.00
V2	sideload	kmac_sideload	1.927m	7.640ms	1	1	100.00
V2	app	kmac_app	4.202m	56.070ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	47.300s	13.742ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.956m	32.616ms	1	1	100.00
V2	error	kmac_error	5.488m	149.671ms	1	1	100.00
V2	key_error	kmac_key_error	4.190s	525.249us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	6.600s	204.581us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	16.010s	3.608ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.290s	16.898us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.169m	30.681ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.750s	70.159us	1	1	100.00
V2	stress_all	kmac_stress_all	3.720s	118.797us	1	1	100.00
V2	intr_test	kmac_intr_test	1.650s	44.732us	1	1	100.00
V2	alert_test	kmac_alert_test	1.680s	71.601us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.060s	209.799us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.060s	209.799us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.750s	19.014us	1	1	100.00
		kmac_csr_rw	1.720s	23.195us	1	1	100.00
		kmac_csr_aliasing	7.010s	401.549us	1	1	100.00
		kmac_same_csr_outstanding	2.090s	66.918us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.750s	19.014us	1	1	100.00
		kmac_csr_rw	1.720s	23.195us	1	1	100.00
		kmac_csr_aliasing	7.010s	401.549us	1	1	100.00
		kmac_same_csr_outstanding	2.090s	66.918us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.820s	67.445us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.820s	67.445us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.820s	67.445us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.820s	67.445us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.660s	168.195us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.091m	15.192ms	1	1	100.00
		kmac_tl_intg_err	1.730s	144.925us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.730s	144.925us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.750s	70.159us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	55.830s	7.403ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.927m	7.640ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.820s	67.445us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.091m	15.192ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.091m	15.192ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.091m	15.192ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	55.830s	7.403ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.750s	70.159us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.091m	15.192ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.814m	16.673ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	55.830s	7.403ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	52.770s	14.355ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.32315880611766023199695292936757964518416402224691990203271552636622290900840
      Line 132, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14354519606 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 14354519606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.2635386304022986638275918603295059618562381442419418534370556412428404472613
      Line 82, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[44] & 'hffffffff)))'
        UVM_ERROR @ 144925027 ps: (kmac_csr_assert_fpv.sv:520) [ASSERT FAILED] prefix_5_rd_A
        UVM_INFO @ 144925027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---