KMAC/UNMASKED Simulation Results

Tuesday May 20 2025 17:03:23 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	3.240s	76.741us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.010s	33.033us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.770s	29.945us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.880s	289.936us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.910s	524.237us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.900s	223.767us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.770s	29.945us	1	1	100.00
		kmac_csr_aliasing	5.910s	524.237us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.560s	36.452us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.080s	36.050us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	19.068m	240.533ms	1	1	100.00
V2	burst_write	kmac_burst_write	2.482m	9.396ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	18.817m	17.658ms	1	1	100.00
		kmac_test_vectors_sha3_256	25.390s	1.675ms	1	1	100.00
		kmac_test_vectors_sha3_384	13.420m	37.434ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.430s	1.101ms	1	1	100.00
		kmac_test_vectors_shake_128	29.150m	144.262ms	1	1	100.00
		kmac_test_vectors_shake_256	1.102m	5.771ms	1	1	100.00
		kmac_test_vectors_kmac	2.600s	270.003us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.160s	50.990us	1	1	100.00
V2	sideload	kmac_sideload	3.232m	10.453ms	1	1	100.00
V2	app	kmac_app	52.460s	1.880ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.081m	13.190ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.385m	44.523ms	1	1	100.00
V2	error	kmac_error	3.534m	85.625ms	1	1	100.00
V2	key_error	kmac_key_error	3.630s	2.388ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.020s	1.039ms	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	15.770s	825.236us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	17.300s	1.301ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	30.540s	5.897ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.970s	53.381us	1	1	100.00
V2	stress_all	kmac_stress_all	15.670s	356.740us	1	1	100.00
V2	intr_test	kmac_intr_test	1.800s	13.829us	1	1	100.00
V2	alert_test	kmac_alert_test	1.800s	53.130us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.950s	181.905us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.950s	181.905us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.010s	33.033us	1	1	100.00
		kmac_csr_rw	1.770s	29.945us	1	1	100.00
		kmac_csr_aliasing	5.910s	524.237us	1	1	100.00
		kmac_same_csr_outstanding	2.070s	24.918us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.010s	33.033us	1	1	100.00
		kmac_csr_rw	1.770s	29.945us	1	1	100.00
		kmac_csr_aliasing	5.910s	524.237us	1	1	100.00
		kmac_same_csr_outstanding	2.070s	24.918us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.170s	76.427us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.170s	76.427us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.170s	76.427us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.170s	76.427us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.690s	33.743us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	19.230s	15.343ms	1	1	100.00
		kmac_tl_intg_err	2.840s	457.145us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.840s	457.145us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.970s	53.381us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	3.240s	76.741us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.232m	10.453ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.170s	76.427us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	19.230s	15.343ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	19.230s	15.343ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	19.230s	15.343ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	3.240s	76.741us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.970s	53.381us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	19.230s	15.343ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.705m	25.435ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	3.240s	76.741us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.200s	47.156us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.65817463601655284986648048727899999914323470587846264818435298614680111195211
      Line 81, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  47156437 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
        UVM_INFO @  47156437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.109745905358076687395142952260918967964745371594896886837047195191828736577346
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[49] & 'hffffffff)))'
        UVM_ERROR @  33743060 ps: (kmac_csr_assert_fpv.sv:545) [ASSERT FAILED] prefix_10_rd_A
        UVM_INFO @  33743060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---