ROM_CTRL/32KB Simulation Results

Tuesday May 20 2025 17:03:23 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 4.980s 135.954us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 6.960s 553.311us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.520s 298.826us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.020s 371.456us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.160s 213.705us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 4.760s 819.639us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.520s 298.826us 1 1 100.00
rom_ctrl_csr_aliasing 4.160s 213.705us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.790s 385.318us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.290s 170.838us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.100s 515.143us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 11.850s 1.522ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 6.980s 389.113us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 5.640s 164.356us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 7.210s 621.845us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 7.210s 621.845us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 6.960s 553.311us 1 1 100.00
rom_ctrl_csr_rw 4.520s 298.826us 1 1 100.00
rom_ctrl_csr_aliasing 4.160s 213.705us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.440s 248.880us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 6.960s 553.311us 1 1 100.00
rom_ctrl_csr_rw 4.520s 298.826us 1 1 100.00
rom_ctrl_csr_aliasing 4.160s 213.705us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.440s 248.880us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 47.500s 7.498ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 15.270s 564.914us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.896m 986.481us 1 1 100.00
rom_ctrl_tl_intg_err 40.560s 373.577us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.896m 986.481us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.896m 986.481us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 47.500s 7.498ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 47.500s 7.498ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 47.500s 7.498ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 47.500s 7.498ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 47.500s 7.498ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.896m 986.481us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.896m 986.481us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 4.980s 135.954us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 4.980s 135.954us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 4.980s 135.954us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 40.560s 373.577us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 47.500s 7.498ms 1 1 100.00
rom_ctrl_kmac_err_chk 6.980s 389.113us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 47.500s 7.498ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 47.500s 7.498ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 47.500s 7.498ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 15.270s 564.914us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.896m 986.481us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.242m 6.300ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00