ROM_CTRL/64KB Simulation Results

Tuesday May 20 2025 17:03:23 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 10.240s 1.103ms 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 11.140s 1.736ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.500s 1.690ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 8.460s 291.701us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.090s 1.024ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.870s 224.378us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.500s 1.690ms 1 1 100.00
rom_ctrl_csr_aliasing 7.090s 1.024ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.960s 1.066ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 7.190s 1.497ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.790s 5.146ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 30.560s 1.102ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 16.290s 558.163us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.870s 293.303us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 10.570s 356.378us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 10.570s 356.378us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 11.140s 1.736ms 1 1 100.00
rom_ctrl_csr_rw 7.500s 1.690ms 1 1 100.00
rom_ctrl_csr_aliasing 7.090s 1.024ms 1 1 100.00
rom_ctrl_same_csr_outstanding 10.290s 795.145us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 11.140s 1.736ms 1 1 100.00
rom_ctrl_csr_rw 7.500s 1.690ms 1 1 100.00
rom_ctrl_csr_aliasing 7.090s 1.024ms 1 1 100.00
rom_ctrl_same_csr_outstanding 10.290s 795.145us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 2.907m 6.237ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 23.520s 765.216us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 5.038m 1.517ms 1 1 100.00
rom_ctrl_tl_intg_err 1.213m 485.574us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 5.038m 1.517ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 5.038m 1.517ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.907m 6.237ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.907m 6.237ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.907m 6.237ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.907m 6.237ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.907m 6.237ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 5.038m 1.517ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 5.038m 1.517ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 10.240s 1.103ms 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 10.240s 1.103ms 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 10.240s 1.103ms 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.213m 485.574us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.907m 6.237ms 1 1 100.00
rom_ctrl_kmac_err_chk 16.290s 558.163us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 2.907m 6.237ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 2.907m 6.237ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 2.907m 6.237ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 23.520s 765.216us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 5.038m 1.517ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.787m 4.182ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00