RV_TIMER Simulation Results

Tuesday May 20 2025 17:03:23 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.630s	15.191us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.540s	15.300us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.520s	15.444us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.880s	947.163us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.970s	23.356us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.740s	40.608us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.520s	15.444us	1	1	100.00
		rv_timer_csr_aliasing	1.970s	23.356us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.590s	116.000us	1	1	100.00
V2	disabled	rv_timer_disabled	1.720s	1.450ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	6.339m	302.988ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	6.339m	302.988ms	1	1	100.00
V2	stress	rv_timer_stress_all	1.570s	82.630us	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.440s	17.103us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.480s	18.609us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.880s	45.542us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.880s	45.542us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.540s	15.300us	1	1	100.00
		rv_timer_csr_rw	1.520s	15.444us	1	1	100.00
		rv_timer_csr_aliasing	1.970s	23.356us	1	1	100.00
		rv_timer_same_csr_outstanding	1.590s	20.831us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.540s	15.300us	1	1	100.00
		rv_timer_csr_rw	1.520s	15.444us	1	1	100.00
		rv_timer_csr_aliasing	1.970s	23.356us	1	1	100.00
		rv_timer_same_csr_outstanding	1.590s	20.831us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.880s	506.513us	1	1	100.00
		rv_timer_tl_intg_err	1.760s	53.823us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.760s	53.823us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	28.890s	8.927ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.480s	22.464us	1	1	100.00
		rv_timer_max	1.450s	79.923us	1	1	100.00
		TOTAL			19	19	100.00