SPI_DEVICE/1R1W Simulation Results

Tuesday May 20 2025 17:03:23 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.344m	5.027ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.000s	64.476us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.740s	71.627us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	26.930s	2.716ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.830s	2.534ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.450s	211.295us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.740s	71.627us	1	1	100.00
		spi_device_csr_aliasing	11.830s	2.534ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.550s	24.832us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.430s	499.870us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.630s	20.543us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	2.010s	7.420us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.880s	7.188us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.860s	160.764us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.860s	160.764us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.640s	2.095ms	1	1	100.00
		spi_device_tpm_sts_read	2.210s	545.310us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	8.440s	3.077ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	5.810s	4.037ms	1	1	100.00
		spi_device_flash_all	1.229m	11.706ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	7.610s	58.330ms	1	1	100.00
		spi_device_flash_all	1.229m	11.706ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	7.610s	58.330ms	1	1	100.00
		spi_device_flash_all	1.229m	11.706ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.229m	11.706ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.570s	282.251us	1	1	100.00
		spi_device_flash_all	1.229m	11.706ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.570s	282.251us	1	1	100.00
		spi_device_flash_all	1.229m	11.706ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.570s	282.251us	1	1	100.00
		spi_device_flash_all	1.229m	11.706ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.570s	282.251us	1	1	100.00
		spi_device_flash_all	1.229m	11.706ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.570s	282.251us	1	1	100.00
		spi_device_flash_all	1.229m	11.706ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	22.500s	22.815ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	1.478m	34.758ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.478m	34.758ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.478m	34.758ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	20.260s	3.448ms	1	1	100.00
		spi_device_read_buffer_direct	4.930s	150.572us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.478m	34.758ms	1	1	100.00
		spi_device_flash_all	1.229m	11.706ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.229m	11.706ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.229m	11.706ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.990s	1.155ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.990s	1.155ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.344m	5.027ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	2.022m	60.550ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.830s	191.183us	1	1	100.00
V2	alert_test	spi_device_alert_test	2.040s	32.175us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.910s	17.311us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.760s	897.052us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.760s	897.052us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.000s	64.476us	1	1	100.00
		spi_device_csr_rw	2.740s	71.627us	1	1	100.00
		spi_device_csr_aliasing	11.830s	2.534ms	1	1	100.00
		spi_device_same_csr_outstanding	2.640s	314.688us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.000s	64.476us	1	1	100.00
		spi_device_csr_rw	2.740s	71.627us	1	1	100.00
		spi_device_csr_aliasing	11.830s	2.534ms	1	1	100.00
		spi_device_same_csr_outstanding	2.640s	314.688us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.530s	127.869us	1	1	100.00
		spi_device_tl_intg_err	18.490s	1.015ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	18.490s	1.015ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	35.470s	2.185ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.60893903893685585790477546970448790274624832979439060712763636397462492773026
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4369707 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[21])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4369707 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4369707 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[917])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.75920628896789169256674803359437389131475730560048477531302734425267063621575
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   4625351 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x708259 [11100001000001001011001] vs 0x0 [0])
        UVM_ERROR @   4645351 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7ddb5 [1111101110110110101] vs 0x0 [0])
        UVM_ERROR @   4717351 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x115890 [100010101100010010000] vs 0x0 [0])
        UVM_ERROR @   4767351 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2e805a [1011101000000001011010] vs 0x0 [0])
        UVM_ERROR @   4815351 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa6ecfa [101001101110110011111010] vs 0x0 [0])