SRAM_CTRL/MAIN Simulation Results

Tuesday May 20 2025 17:03:23 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 14.450s 5.977ms 1 1 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 1.470s 17.005us 1 1 100.00
V1 csr_rw sram_ctrl_csr_rw 1.770s 15.410us 1 1 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.640s 42.624us 1 1 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 1.680s 46.032us 1 1 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 4.030s 697.534us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 1.770s 15.410us 1 1 100.00
sram_ctrl_csr_aliasing 1.680s 46.032us 1 1 100.00
V1 mem_walk sram_ctrl_mem_walk 2.091m 10.355ms 1 1 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 1.017m 10.719ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 multiple_keys sram_ctrl_multiple_keys 11.156m 64.190ms 1 1 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 4.918m 12.400ms 1 1 100.00
V2 bijection sram_ctrl_bijection 32.953m 661.316ms 1 1 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 6.389m 13.898ms 1 1 100.00
V2 lc_escalation sram_ctrl_lc_escalation 10.650s 2.376ms 1 1 100.00
V2 executable sram_ctrl_executable 3.940m 16.007ms 1 1 100.00
V2 partial_access sram_ctrl_partial_access 6.240s 1.049ms 1 1 100.00
sram_ctrl_partial_access_b2b 5.865m 39.853ms 1 1 100.00
V2 max_throughput sram_ctrl_max_throughput 25.210s 760.186us 1 1 100.00
sram_ctrl_throughput_w_partial_write 39.540s 781.753us 1 1 100.00
sram_ctrl_throughput_w_readback 15.610s 792.456us 1 1 100.00
V2 regwen sram_ctrl_regwen 4.350m 10.094ms 1 1 100.00
V2 ram_cfg sram_ctrl_ram_cfg 3.130s 695.164us 1 1 100.00
V2 stress_all sram_ctrl_stress_all 27.627m 33.472ms 1 1 100.00
V2 alert_test sram_ctrl_alert_test 1.580s 44.764us 1 1 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.680s 1.145ms 1 1 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.680s 1.145ms 1 1 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 1.470s 17.005us 1 1 100.00
sram_ctrl_csr_rw 1.770s 15.410us 1 1 100.00
sram_ctrl_csr_aliasing 1.680s 46.032us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.740s 46.328us 1 1 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 1.470s 17.005us 1 1 100.00
sram_ctrl_csr_rw 1.770s 15.410us 1 1 100.00
sram_ctrl_csr_aliasing 1.680s 46.032us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.740s 46.328us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 35.920s 20.745ms 1 1 100.00
V2S tl_intg_err sram_ctrl_sec_cm 1.810s 10.091us 0 1 0.00
sram_ctrl_tl_intg_err 2.780s 226.248us 1 1 100.00
V2S prim_count_check sram_ctrl_sec_cm 1.810s 10.091us 0 1 0.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.780s 226.248us 1 1 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 4.350m 10.094ms 1 1 100.00
V2S sec_cm_readback_config_regwen sram_ctrl_regwen 4.350m 10.094ms 1 1 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 1.770s 15.410us 1 1 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 3.940m 16.007ms 1 1 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 3.940m 16.007ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 3.940m 16.007ms 1 1 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 10.650s 2.376ms 1 1 100.00
V2S sec_cm_prim_ram_ctrl_mubi sram_ctrl_mubi_enc_err 5.300s 702.996us 1 1 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 35.920s 20.745ms 1 1 100.00
V2S sec_cm_mem_readback sram_ctrl_readback_err 6.150s 1.332ms 1 1 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 14.450s 5.977ms 1 1 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 14.450s 5.977ms 1 1 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 3.940m 16.007ms 1 1 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 1.810s 10.091us 0 1 0.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 10.650s 2.376ms 1 1 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 1.810s 10.091us 0 1 0.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 1.810s 10.091us 0 1 0.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 14.450s 5.977ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 1.810s 10.091us 0 1 0.00
V2S TOTAL 4 5 80.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 31.540s 1.383ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 31 96.77

Failure Buckets