SRAM_CTRL/RET Simulation Results

Tuesday May 20 2025 17:03:23 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	9.620s	77.823us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.570s	25.552us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.590s	10.806us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.500s	1.342ms	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.740s	47.127us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.240s	68.077us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.590s	10.806us	1	1	100.00
		sram_ctrl_csr_aliasing	1.740s	47.127us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.320s	1.081ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.390s	93.409us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	multiple_keys	sram_ctrl_multiple_keys	3.959m	7.586ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.181m	1.882ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	52.670s	6.401ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.059m	4.958ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.290s	491.932us	1	1	100.00
V2	executable	sram_ctrl_executable	6.775m	6.718ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	12.430s	298.613us	1	1	100.00
		sram_ctrl_partial_access_b2b	2.436m	10.367ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.960s	170.045us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	50.430s	159.207us	1	1	100.00
		sram_ctrl_throughput_w_readback	12.040s	934.038us	1	1	100.00
V2	regwen	sram_ctrl_regwen	10.479m	14.601ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.580s	81.503us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	27.689m	17.619ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.560s	21.420us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.440s	183.189us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.440s	183.189us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.570s	25.552us	1	1	100.00
		sram_ctrl_csr_rw	1.590s	10.806us	1	1	100.00
		sram_ctrl_csr_aliasing	1.740s	47.127us	1	1	100.00
		sram_ctrl_same_csr_outstanding	2.050s	33.002us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.570s	25.552us	1	1	100.00
		sram_ctrl_csr_rw	1.590s	10.806us	1	1	100.00
		sram_ctrl_csr_aliasing	1.740s	47.127us	1	1	100.00
		sram_ctrl_same_csr_outstanding	2.050s	33.002us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.460s	492.735us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.550s	19.159us	0	1	0.00
		sram_ctrl_tl_intg_err	2.010s	93.996us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.550s	19.159us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.010s	93.996us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	10.479m	14.601ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	10.479m	14.601ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.590s	10.806us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	6.775m	6.718ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	6.775m	6.718ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	6.775m	6.718ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.290s	491.932us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.280s	134.328us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.460s	492.735us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.010s	27.338us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	9.620s	77.823us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	9.620s	77.823us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	6.775m	6.718ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.550s	19.159us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.290s	491.932us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.550s	19.159us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.550s	19.159us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	9.620s	77.823us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.550s	19.159us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.325m	846.028us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.111891482763634845120324853077126914040667869182251049172328948306101289799837
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  19158860 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  19158860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.sram_ctrl_csr_mem_rw_with_rand_reset.91240850925899912146024237968720505665379663979961999685938911742517234163608
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  68077185 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (4 [0x4] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
        UVM_INFO @  68077185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---