UART Simulation Results

Tuesday May 20 2025 17:03:23 UTC

GitHub Revision: 0463149

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.550s	498.864us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.390s	47.677us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.710s	16.040us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.150s	161.536us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.850s	51.693us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.360s	21.372us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.710s	16.040us	1	1	100.00
		uart_csr_aliasing	1.850s	51.693us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	38.880s	30.807ms	1	1	100.00
V2	parity	uart_smoke	2.550s	498.864us	1	1	100.00
		uart_tx_rx	38.880s	30.807ms	1	1	100.00
V2	parity_error	uart_intr	6.260s	7.632ms	1	1	100.00
		uart_rx_parity_err	5.009m	191.639ms	1	1	100.00
V2	watermark	uart_tx_rx	38.880s	30.807ms	1	1	100.00
		uart_intr	6.260s	7.632ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.480m	83.242ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	32.390s	343.919ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	15.680s	36.480ms	1	1	100.00
V2	rx_frame_err	uart_intr	6.260s	7.632ms	1	1	100.00
V2	rx_break_err	uart_intr	6.260s	7.632ms	1	1	100.00
V2	rx_timeout	uart_intr	6.260s	7.632ms	1	1	100.00
V2	perf	uart_perf	7.371m	19.061ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.860s	9.742ms	1	1	100.00
V2	line_loopback	uart_loopback	3.860s	9.742ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	2.639m	127.164ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.230s	5.726ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.410s	2.069ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	12.320s	3.048ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	1.643m	53.463ms	1	1	100.00
V2	stress_all	uart_stress_all	3.456m	284.915ms	1	1	100.00
V2	alert_test	uart_alert_test	1.500s	24.720us	1	1	100.00
V2	intr_test	uart_intr_test	1.480s	131.955us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.820s	206.322us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.820s	206.322us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.390s	47.677us	1	1	100.00
		uart_csr_rw	1.710s	16.040us	1	1	100.00
		uart_csr_aliasing	1.850s	51.693us	1	1	100.00
		uart_same_csr_outstanding	1.630s	19.448us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.390s	47.677us	1	1	100.00
		uart_csr_rw	1.710s	16.040us	1	1	100.00
		uart_csr_aliasing	1.850s	51.693us	1	1	100.00
		uart_same_csr_outstanding	1.630s	19.448us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.570s	120.366us	1	1	100.00
		uart_tl_intg_err	1.800s	118.512us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.800s	118.512us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	32.980s	24.166ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00