CHIP Simulation Results

Tuesday May 20 2025 17:03:23 UTC

GitHub Revision: `0463149`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.502m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.502m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	46.151s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	28.019s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	11.902s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.999m	4.901ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.999m	4.901ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.999m	4.901ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	41.170s	10.380us	0	1	0.00
		chip_sw_example_manufacturer	2.550m		0	1	0.00
		chip_sw_example_concurrency	4.543m	4.584ms	1	1	100.00
		chip_sw_uart_smoketest_signed	18.900s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	10.050s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	11.310s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	11.310s		0	1	0.00
V1	xbar_smoke	xbar_smoke	10.740s	11.756us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.368m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	12.341m	8.767ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	5.342m	5.461ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	13.459s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	16.102s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	16.062s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	17.034s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.560s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.560s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.451m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.333m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.298m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.298m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.600m	3.210ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.464m	5.124ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.299m	13.903ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.258s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.094s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	18.150m	19.621ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.850m	5.833ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	21.049m	18.015ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	21.049m	18.015ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.135s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.153m	5.225ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.153m	5.225ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	7.686m	18.017ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.446m	3.825ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	4.597m	3.745ms	1	1	100.00
		chip_sw_aes_idle	4.484m	4.118ms	1	1	100.00
		chip_sw_hmac_enc_idle	5.069m	5.717ms	1	1	100.00
		chip_sw_kmac_idle	4.267m	4.587ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	12.443m	12.015ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	12.348m	12.018ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	11.806m	12.015ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	12.443m	12.015ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	11.351s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.881s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.462s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.540s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.948s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.162s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.958s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	11.351s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.881s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.462s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.540s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.948s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.162s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.958s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	13.459s		0	1	0.00
		chip_sw_aes_enc_jitter_en	52.020s	10.180us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	46.690s	10.380us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	48.990s	10.280us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	55.270s	10.260us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	16.359s		0	1	0.00
		chip_sw_clkmgr_jitter	3.452m	4.603ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.073m	3.815ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	16.222s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	1.074m	10.120us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	48.070s	10.240us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	46.550s	10.200us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	53.400s	10.180us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	53.740s	10.300us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	13.250s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	12.105s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.187s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	13.547s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	20.018m	15.962ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.439m	14.667ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	5.153m	5.225ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.918s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.439m	14.667ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	10.373s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	15.677s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	14.267s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	10.475s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	11.517s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	20.018m	15.962ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.299m	13.903ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	25.218m	20.017ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.018m	6.734ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	10.259m	10.697ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.252m	4.434ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	20.018m	15.962ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	10.499s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	14.162s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	20.018m	15.962ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	14.117s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	10.259m	10.697ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	12.164s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	11.796s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.313s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.177s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.829s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	13.490s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	14.162s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	13.634s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	22.652s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	13.634s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	13.634s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	13.634s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	7.436m	9.380ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	16.630s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	14.997s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	12.373s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	15.419s		0	1	0.00
		chip_sw_lc_ctrl_transition	13.634s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	7.966m	8.932ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	9.930m	13.472ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.758s		0	1	0.00
		chip_prim_tl_access	8.044m	11.663ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	11.351s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.881s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.462s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.540s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.948s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.162s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.958s		0	1	0.00
		chip_rv_dm_lc_disabled	18.150m	19.621ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.137m	3.904ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	52.020s	10.180us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.662m	5.020ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.484m	4.118ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.117m	3.522ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	46.690s	10.380us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.069m	5.717ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.481m	5.097ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.752m	4.710ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	55.270s	10.260us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	7.966m	8.932ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	13.634s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	39.350s	10.140us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.984m	5.838ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.267m	4.587ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.403s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.403s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.810s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.380m	5.919ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	13.084s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	7.966m	8.932ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	48.990s	10.280us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	12.746s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	13.459s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	4.597m	3.745ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	4.597m	3.745ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	4.597m	3.745ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.594m	5.485ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.930m	13.472ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.930m	13.472ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.408m	7.695ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	16.359s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.758s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	20.018m	15.962ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.298m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	13.634s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.594m	5.485ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.966m	8.932ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.408m	7.695ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.683m	5.655ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.594m	5.485ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.966m	8.932ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.408m	7.695ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.683m	5.655ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	13.634s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.343s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	22.652s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	16.630s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	14.997s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	12.373s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	15.419s		0	1	0.00
		chip_sw_lc_ctrl_transition	13.634s		0	1	0.00
		chip_prim_tl_access	8.044m	11.663ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	8.044m	11.663ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	12.029s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	12.616s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	12.105s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	13.459s		0	1	0.00
		chip_sw_aes_enc_jitter_en	52.020s	10.180us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	46.690s	10.380us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	48.990s	10.280us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	55.270s	10.260us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	16.359s		0	1	0.00
		chip_sw_clkmgr_jitter	3.452m	4.603ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	6.374m	7.401ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	6.374m	7.401ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	3.464m	3.789ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	5.729m	5.441ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.526m	5.088ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.547m	6.476ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.708m	4.021ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.640m	4.925ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.683m	5.655ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	25.218m	20.017ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	25.218m	20.017ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.365m	4.025ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.468m	3.568ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.602m	5.130ms	1	1	100.00
		chip_sw_csrng_smoketest	3.746m	4.935ms	1	1	100.00
		chip_sw_gpio_smoketest	3.336m	4.598ms	1	1	100.00
		chip_sw_hmac_smoketest	3.981m	3.714ms	1	1	100.00
		chip_sw_kmac_smoketest	3.582m	5.332ms	1	1	100.00
		chip_sw_otbn_smoketest	4.300m	5.489ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	2.905m	3.715ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.157m	4.526ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.060m	5.079ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.601m	4.134ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.996m	3.533ms	1	1	100.00
		chip_sw_uart_smoketest	3.808m	5.381ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	27.397s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	18.900s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.368m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.663s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.811m	4.064ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.220m	4.945ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.694m	5.572ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.049m	6.771ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	11.986s		0	1	0.00
		chip_rv_dm_lc_disabled	18.150m	19.621ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	14.572s		0	1	0.00
		chip_sw_lc_walkthrough_prod	14.061s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	17.084s		0	1	0.00
		chip_sw_lc_walkthrough_rma	11.249s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	11.986s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	15.004s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	11.928s		0	1	0.00
		rom_volatile_raw_unlock	11.310s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.556s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	37.818s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.240m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.100m	3.342ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.100m	3.342ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	11.310s		0	1	0.00
		chip_same_csr_outstanding	14.900s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	11.310s		0	1	0.00
		chip_same_csr_outstanding	14.900s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	1.218m	202.755us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.120s	13.808us	1	1	100.00
		xbar_smoke_large_delays	4.900m	2.522ms	1	1	100.00
		xbar_smoke_slow_rsp	4.917m	1.855ms	1	1	100.00
		xbar_random_zero_delays	47.130s	46.195us	1	1	100.00
		xbar_random_large_delays	13.808m	6.991ms	1	1	100.00
		xbar_random_slow_rsp	13.477m	4.915ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	31.570s	62.303us	1	1	100.00
		xbar_error_and_unmapped_addr	1.023m	135.222us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	3.394m	536.076us	1	1	100.00
		xbar_error_and_unmapped_addr	1.023m	135.222us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.509m	418.864us	1	1	100.00
		xbar_access_same_device_slow_rsp	37.710m	14.712ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.592m	277.834us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	11.723m	1.668ms	1	1	100.00
		xbar_stress_all_with_error	18.152m	3.039ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	7.437m	842.168us	1	1	100.00
		xbar_stress_all_with_reset_error	12.233m	563.167us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.960s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	12.927s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	11.965s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	12.859s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	11.108s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.573s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	10.635s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.002s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.409s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.281s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.919s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.678s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.111s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.862s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.156s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	12.116s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.412s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.788s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	13.440s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	11.435s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	12.151s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	11.490s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	12.930s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	11.763s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	11.623s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.209s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.565s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.760s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.476s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.334s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.737s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.760s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.870s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.721s		0	1	0.00
		rom_e2e_asm_init_dev	12.066s		0	1	0.00
		rom_e2e_asm_init_prod	11.702s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.287s		0	1	0.00
		rom_e2e_asm_init_rma	11.230s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.783s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.183s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.565s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.213s		0	1	0.00
V2		TOTAL			65	205	31.71
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.555m	4.346ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.420m	3.921ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	10.745s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.186s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.512s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.904s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	20.018m	15.962ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	15.046s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	16.335m	12.137ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	12.824s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	11.704s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	10.745s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.186s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.512s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	10.997s		0	1	0.00
		rom_e2e_jtag_inject_dev	10.712s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.190s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.081m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	19.356m	12.988ms	1	1	100.00
		chip_plic_all_irqs_0	8.720m	6.905ms	1	1	100.00
		chip_plic_all_irqs_10	9.940m	7.189ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.178m	3.524ms	1	1	100.00
		chip_sw_dma_abort	3.822m	3.758ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.812s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.341s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	10.558s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.615s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.640s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.542s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.649s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	10.631s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.888s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.250s		0	1	0.00
		chip_sw_mbx_smoketest	3.713m	5.113ms	1	1	100.00
		TOTAL			76	247	30.77

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.99758661112583596077834223920713175714121043957476775982205975975376309672776
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (3f2002)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 142.305s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.11868130335435065856843967381776002199188408816559424549168914725011397993768
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (cd6763)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 127.196s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.109041345758602206977158998553507963929364465701350724551870966097780335644275
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (2f19a4)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 136.376s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.60577779764819931611261312578733901452898036493245880017744554757333629363815
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (318f57)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 129.684s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.1995087959178175241091107751602686088330661937331789237617033082419008852547
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Target //sw/device/tests:uart_tx_rx_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (7fcc5a)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 80.325s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.84195884758118826914938273102749871469475912052299081170136967965269270359148
    Line 425, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.47449831084365006740545855075728430951674634066477271853155979443279495592345
    Line 433, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.86967426556022035597812883444598947964112114660990492878447984140788556902045
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.33218689556399115242707764515486397686699504092890574060076049585072603940381
    Line 412, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.47486439316669699251562478563712036045926814378352617544856389961240572622721
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 4 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.110385892813752143652976899674430443042549430297046230994763773513451374033123
Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12015.155810 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12015.155810 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.59125542607976819324136586832939583850264196232913463864919012120973887819292
Line 428, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12017.904222 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12017.904222 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.73183399061720684900024559751636764076574017421534462995624056159428697143661
Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12015.473956 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12015.473956 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.66398114720401346550953099745406964273203179937814241293325968619170262879910
Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12015.036295 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12015.036295 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.8645979111749367472835029904338686251107184165235937374144439013640572964398
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.97060426640037650414742387107845948925355032296176561368978318875897296545442
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.93801895232616887120892015609394237998474874158271129552353060473608771952266
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.109091224233637112219549155442574465953324384066128849455640641923075383209684
Line 453, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20016.900662 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20016.900662 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.23815351250919214238356252260809315703497852393394279647123366222414025725517
Line 414, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18014.867507 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18014.867507 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.74426861412817245173119284480565975318035473484515817869428324443833760860319
Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18017.472094 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18017.472094 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.64466859344604280816010983515718316518511379837910596425737302232048496164918
Line 486, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 8932.484856 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (83350778846769490356960696631778737872943614675933744165229123363015743002693 [0xb846de77a157ad41f71654fc03e2b11f308ae680b0a7c7eee2e58467c55c5845] vs 9502894479875926835195145448707404750003086801262054021385666936592961047138 [0x1502729a8a77fc0db3400d02ce1247e30ef900faec588aa86bbce4a9ddab0a62])
  UVM_INFO @ 8932.484856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.82917045797044121326126186564245992695485764541022995650471400969359871106354
Line 474, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 9380.016628 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (12362681025384892317662605063184660209572742259981591570837153447514150539388 [0x1b55078cfbc2eefe7ca0e68fad9cea171172bee2b4c2811a212156ddedd0107c] vs 77311137813278005359059990893757756778586387267764660480321794971222313832495 [0xaaec8da6efc0dc997ac2f1b1f66ee6f18d42b445862e2671c13371d9e510902f])
  UVM_INFO @ 9380.016628 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.12242239130049865799206591985218853562626571317037537187030499216423921675716
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3209.972220 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h472112d2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3b  a_opcode: 'h0  a_user: 'h26973  d_param: 'h0  d_source: 'h3b  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3209.972220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.46637182894500370768466146896147184002344407070198190525949394485461076530643
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 5124.312243 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hb72d0ff7  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h20  a_opcode: 'h0  a_user: 'h2696a  d_param: 'h0  d_source: 'h20  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5124.312243 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.13857301907045008222631448091783836847495805673406724708901785915282058765919
    Line 626, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.89305353993228518547738380852919293863539912335171134497104266961930632904738
    Line 455, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5460.908760 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5460.908760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.20618902129375372766030287365524158484684827739201243334780315899256581472391
    Line 666, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 10696.896408 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 10696.896408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.22764455525342956704207598974114886387606917132855325935278249976913484512279
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 3788.752180 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3788.752180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.40898636249490217647769514426951456617157216200227625227897645781673935497091
    Line 429, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 5440.789896 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 5440.789896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.71171402375401752736099495577954438411191456849845102445333462056474985853823
    Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 5224.753144 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 5224.753144 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.3993059998189212474524493131576493264710872921198501445739547376002992227184
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6475.858448 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6475.858448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.72784443202722381132321082330708718481688811200486047746361235462115100497634
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36962) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.2821081470531169263187385047206063307734894980155528209097900459047658673826
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3342.492760 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36962) { a_addr: 'h405a0  a_data: 'hcd840ee1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h4  a_user: 'h19d82  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3342.492760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.65601055283452896235754631894296642008117610380270117890872454778877043232652
    Line 405, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 13903.157756 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 13903.157756 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.63107768369910022156190431899405149522365165035332810634147577667328766103153
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.63511963869500750780539566163568655608819684341276968227957275534024028882672
    Line 425, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 3758.361864 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 3758.361864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```