DMA Simulation Results

Wednesday May 21 2025 17:01:47 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	7.000s	1.226ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	9.000s	549.166us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	9.000s	3.321ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	19.024us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	65.760us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	9.000s	2.801ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	6.000s	228.920us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	30.885us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	65.760us	1	1	100.00
		dma_csr_aliasing	6.000s	228.920us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.450m	4.889ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	17.567m	110.672ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	4.583m	88.050ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	2.533m	51.750ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	17.567m	110.672ms	1	1	100.00
V2	dma_abort	dma_abort	7.000s	1.088ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	3.800m	18.043ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	39.775us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	6.000s	100.774us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	6.000s	100.774us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	19.024us	1	1	100.00
		dma_csr_rw	4.000s	65.760us	1	1	100.00
		dma_csr_aliasing	6.000s	228.920us	1	1	100.00
		dma_same_csr_outstanding	5.000s	99.640us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	19.024us	1	1	100.00
		dma_csr_rw	4.000s	65.760us	1	1	100.00
		dma_csr_aliasing	6.000s	228.920us	1	1	100.00
		dma_same_csr_outstanding	5.000s	99.640us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	17.000s	675.318us	1	1	100.00
		dma_generic_stress	2.533m	51.750ms	1	1	100.00
		dma_handshake_stress	17.567m	110.672ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	5.000s	96.600us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.267m	7.318ms	1	1	100.00
		dma_longer_transfer	6.000s	505.112us	1	1	100.00
		TOTAL			21	21	100.00