EDN Simulation Results

Wednesday May 21 2025 17:01:47 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	2.020s	25.625us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.890s	16.188us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.810s	28.753us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.110s	86.988us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	2.290s	42.823us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.430s	203.784us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.810s	28.753us	1	1	100.00
		edn_csr_aliasing	2.290s	42.823us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.990s	51.919us	1	1	100.00
V2	csrng_commands	edn_genbits	1.990s	51.919us	1	1	100.00
V2	genbits	edn_genbits	1.990s	51.919us	1	1	100.00
V2	interrupts	edn_intr	1.700s	30.923us	1	1	100.00
V2	alerts	edn_alert	1.930s	24.124us	1	1	100.00
V2	errs	edn_err	2.210s	24.490us	1	1	100.00
V2	disable	edn_disable	1.880s	13.287us	1	1	100.00
		edn_disable_auto_req_mode	1.910s	100.738us	1	1	100.00
V2	stress_all	edn_stress_all	4.110s	309.746us	1	1	100.00
V2	intr_test	edn_intr_test	1.780s	13.142us	1	1	100.00
V2	alert_test	edn_alert_test	1.850s	15.599us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.100s	91.315us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.100s	91.315us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.890s	16.188us	1	1	100.00
		edn_csr_rw	1.810s	28.753us	1	1	100.00
		edn_csr_aliasing	2.290s	42.823us	1	1	100.00
		edn_same_csr_outstanding	1.960s	67.147us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.890s	16.188us	1	1	100.00
		edn_csr_rw	1.810s	28.753us	1	1	100.00
		edn_csr_aliasing	2.290s	42.823us	1	1	100.00
		edn_same_csr_outstanding	1.960s	67.147us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	9.160s	7.543ms	1	1	100.00
		edn_tl_intg_err	2.140s	179.886us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.750s	56.410us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.930s	24.124us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	9.160s	7.543ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	9.160s	7.543ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	9.160s	7.543ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	9.160s	7.543ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.930s	24.124us	1	1	100.00
		edn_sec_cm	9.160s	7.543ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.930s	24.124us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.140s	179.886us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.415m	34.154ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00