HMAC Simulation Results

Wednesday May 21 2025 17:01:47 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 2.970s 264.532us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.710s 132.508us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.660s 165.828us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 8.410s 1.109ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.030s 163.536us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.180s 97.174us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.660s 165.828us 1 1 100.00
hmac_csr_aliasing 3.030s 163.536us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 25.280s 2.645ms 1 1 100.00
V2 back_pressure hmac_back_pressure 37.610s 3.399ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.840s 2.085ms 1 1 100.00
hmac_test_sha384_vectors 6.351m 13.090ms 1 1 100.00
hmac_test_sha512_vectors 19.020s 209.658us 1 1 100.00
hmac_test_hmac256_vectors 9.490s 1.338ms 1 1 100.00
hmac_test_hmac384_vectors 9.620s 314.436us 1 1 100.00
hmac_test_hmac512_vectors 10.460s 730.367us 1 1 100.00
V2 burst_wr hmac_burst_wr 13.010s 1.778ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 5.925m 3.684ms 1 1 100.00
V2 error hmac_error 25.700s 2.360ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 43.680s 21.084ms 1 1 100.00
V2 save_and_restore hmac_smoke 2.970s 264.532us 1 1 100.00
hmac_long_msg 25.280s 2.645ms 1 1 100.00
hmac_back_pressure 37.610s 3.399ms 1 1 100.00
hmac_datapath_stress 5.925m 3.684ms 1 1 100.00
hmac_burst_wr 13.010s 1.778ms 1 1 100.00
hmac_stress_all 1.896m 13.572ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 2.970s 264.532us 1 1 100.00
hmac_long_msg 25.280s 2.645ms 1 1 100.00
hmac_back_pressure 37.610s 3.399ms 1 1 100.00
hmac_datapath_stress 5.925m 3.684ms 1 1 100.00
hmac_wipe_secret 43.680s 21.084ms 1 1 100.00
hmac_test_sha256_vectors 8.840s 2.085ms 1 1 100.00
hmac_test_sha384_vectors 6.351m 13.090ms 1 1 100.00
hmac_test_sha512_vectors 19.020s 209.658us 1 1 100.00
hmac_test_hmac256_vectors 9.490s 1.338ms 1 1 100.00
hmac_test_hmac384_vectors 9.620s 314.436us 1 1 100.00
hmac_test_hmac512_vectors 10.460s 730.367us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 2.970s 264.532us 1 1 100.00
hmac_long_msg 25.280s 2.645ms 1 1 100.00
hmac_back_pressure 37.610s 3.399ms 1 1 100.00
hmac_datapath_stress 5.925m 3.684ms 1 1 100.00
hmac_burst_wr 13.010s 1.778ms 1 1 100.00
hmac_error 25.700s 2.360ms 1 1 100.00
hmac_wipe_secret 43.680s 21.084ms 1 1 100.00
hmac_test_sha256_vectors 8.840s 2.085ms 1 1 100.00
hmac_test_sha384_vectors 6.351m 13.090ms 1 1 100.00
hmac_test_sha512_vectors 19.020s 209.658us 1 1 100.00
hmac_test_hmac256_vectors 9.490s 1.338ms 1 1 100.00
hmac_test_hmac384_vectors 9.620s 314.436us 1 1 100.00
hmac_test_hmac512_vectors 10.460s 730.367us 1 1 100.00
hmac_stress_all 1.896m 13.572ms 1 1 100.00
V2 stress_all hmac_stress_all 1.896m 13.572ms 1 1 100.00
V2 alert_test hmac_alert_test 1.430s 12.643us 1 1 100.00
V2 intr_test hmac_intr_test 1.430s 23.117us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.210s 275.841us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.210s 275.841us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.710s 132.508us 1 1 100.00
hmac_csr_rw 1.660s 165.828us 1 1 100.00
hmac_csr_aliasing 3.030s 163.536us 1 1 100.00
hmac_same_csr_outstanding 2.480s 514.290us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.710s 132.508us 1 1 100.00
hmac_csr_rw 1.660s 165.828us 1 1 100.00
hmac_csr_aliasing 3.030s 163.536us 1 1 100.00
hmac_same_csr_outstanding 2.480s 514.290us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.600s 39.635us 1 1 100.00
hmac_tl_intg_err 3.850s 2.081ms 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.850s 2.081ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 2.970s 264.532us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.730s 168.001us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 8.714m 31.920ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.620s 8.926us 1 1 100.00
TOTAL 28 28 100.00