I2C Simulation Results

Wednesday May 21 2025 17:01:47 UTC

GitHub Revision: `d7d3545`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	15.390s	5.354ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	10.950s	8.343ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.730s	30.308us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.470s	31.579us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.910s	855.807us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.930s	194.991us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.780s	211.967us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.470s	31.579us	1	1	100.00
		i2c_csr_aliasing	1.930s	194.991us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.190s	255.536us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	10.251m	20.962ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	11.257m	18.504ms	1	1	100.00
V2	host_override	i2c_host_override	1.580s	132.507us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	53.700s	3.824ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	52.660s	4.926ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.840s	197.396us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.680s	1.916ms	1	1	100.00
		i2c_host_fifo_reset_rx	9.040s	452.102us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	55.650s	3.221ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	7.470s	563.605us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.590s	177.527us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.080s	2.292ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	6.765m	33.268ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.660s	2.209ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	18.130s	1.536ms	1	1	100.00
		i2c_target_intr_smoke	3.290s	2.740ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.260s	214.450us	1	1	100.00
		i2c_target_fifo_reset_tx	2.190s	356.517us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	6.747m	68.188ms	1	1	100.00
		i2c_target_stress_rd	18.130s	1.536ms	1	1	100.00
		i2c_target_intr_stress_wr	22.320s	5.628ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.490s	5.580ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	5.510s	1.802ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.020s	1.352ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.580s	1.138ms	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.610s	2.104ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.810s	447.993us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	11.257m	18.504ms	1	1	100.00
		i2c_host_perf_precise	9.570s	3.514ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	7.470s	563.605us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	6.500s	663.692us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.110s	525.735us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.660s	2.100ms	1	1	100.00
		i2c_target_nack_txstretch	2.030s	1.165ms	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	5.310s	455.429us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.340s	453.322us	1	1	100.00
V2	alert_test	i2c_alert_test	1.460s	62.541us	1	1	100.00
V2	intr_test	i2c_intr_test	1.520s	76.615us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.560s	137.800us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.560s	137.800us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.730s	30.308us	1	1	100.00
		i2c_csr_rw	1.470s	31.579us	1	1	100.00
		i2c_csr_aliasing	1.930s	194.991us	1	1	100.00
		i2c_same_csr_outstanding	1.790s	24.247us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.730s	30.308us	1	1	100.00
		i2c_csr_rw	1.470s	31.579us	1	1	100.00
		i2c_csr_aliasing	1.930s	194.991us	1	1	100.00
		i2c_same_csr_outstanding	1.790s	24.247us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.350s	100.448us	1	1	100.00
		i2c_sec_cm	1.680s	83.211us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.350s	100.448us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	3.510s	230.374us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.980s	649.190us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	4.890s	200.321us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.4070025056859195149085814071915178805482939721588160639249773044566893414922
Line 214, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 20962195401 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2789864

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.96681286661039821658820595838425674358161369537619086046103340255278876411884
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 649190433 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 649190433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.39996084420521682883524492122066715785336878237944203661527194782725251581602
    Line 87, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 230374016 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 230374016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.64218759274872303496364581001838584567530017257552846562227038567430268714463
    Line 105, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 200321484 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 67 [0x43])
  UVM_INFO @ 200321484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 0.i2c_host_mode_toggle.113915522445604496370263009294824931726622043357520454009513446543052945523114
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 177526541 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x16093794, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 177526541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```