KEYMGR Simulation Results

Wednesday May 21 2025 17:01:47 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	4.120s	206.336us	1	1	100.00
V1	random	keymgr_random	6.360s	1.156ms	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.650s	64.739us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.630s	13.926us	0	1	0.00
V1	csr_bit_bash	keymgr_csr_bit_bash	18.230s	3.714ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	3.590s	252.339us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.060s	65.647us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.630s	13.926us	0	1	0.00
		keymgr_csr_aliasing	3.590s	252.339us	1	1	100.00
V1		TOTAL			5	7	71.43
V2	cfgen_during_op	keymgr_cfg_regwen	40.220s	7.323ms	1	1	100.00
V2	sideload	keymgr_sideload	2.350s	18.297us	1	1	100.00
		keymgr_sideload_kmac	34.750s	5.148ms	1	1	100.00
		keymgr_sideload_aes	27.770s	1.540ms	1	1	100.00
		keymgr_sideload_otbn	4.520s	332.084us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	3.160s	142.163us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.080s	145.918us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	4.240s	104.920us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.960s	886.328us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.660s	213.606us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.290s	318.855us	1	1	100.00
V2	stress_all	keymgr_stress_all	13.400s	852.386us	1	1	100.00
V2	intr_test	keymgr_intr_test	1.620s	8.389us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.600s	36.236us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.480s	26.785us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.480s	26.785us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.650s	64.739us	1	1	100.00
		keymgr_csr_rw	1.630s	13.926us	0	1	0.00
		keymgr_csr_aliasing	3.590s	252.339us	1	1	100.00
		keymgr_same_csr_outstanding	2.180s	144.678us	0	1	0.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.650s	64.739us	1	1	100.00
		keymgr_csr_rw	1.630s	13.926us	0	1	0.00
		keymgr_csr_aliasing	3.590s	252.339us	1	1	100.00
		keymgr_same_csr_outstanding	2.180s	144.678us	0	1	0.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	6.820s	1.128ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	6.820s	1.128ms	1	1	100.00
		keymgr_tl_intg_err	1.780s	8.744us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.190s	214.072us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.190s	214.072us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.190s	214.072us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.190s	214.072us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	4.770s	433.789us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	6.820s	1.128ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	6.820s	1.128ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	1.780s	8.744us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.190s	214.072us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	40.220s	7.323ms	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	6.360s	1.156ms	1	1	100.00
		keymgr_csr_rw	1.630s	13.926us	0	1	0.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	6.360s	1.156ms	1	1	100.00
		keymgr_csr_rw	1.630s	13.926us	0	1	0.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	6.360s	1.156ms	1	1	100.00
		keymgr_csr_rw	1.630s	13.926us	0	1	0.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.080s	145.918us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.660s	213.606us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.660s	213.606us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	6.360s	1.156ms	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.540s	28.916us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	6.820s	1.128ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	6.820s	1.128ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	6.820s	1.128ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	7.490s	521.057us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.080s	145.918us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	6.820s	1.128ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	6.820s	1.128ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	6.820s	1.128ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	7.490s	521.057us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	7.490s	521.057us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	6.820s	1.128ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	7.490s	521.057us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	6.820s	1.128ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	7.490s	521.057us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	12.170s	567.800us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	30	86.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 4 failures:

  • Test keymgr_tl_intg_err has 1 failures.

    • 0.keymgr_tl_intg_err.77760000048689490905209443297813635246286738705251955766859944274636542122907
      Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
        UVM_ERROR @   8744413 ps: (keymgr_csr_assert_fpv.sv:464) [ASSERT FAILED] attest_sw_binding_6_rd_A
        UVM_INFO @   8744413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_rw has 1 failures.

    • 0.keymgr_csr_rw.94996232322088580122977674860162428602002397313146883045467176163321216341449
      Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[9] & 'hffffffff)))'
        UVM_ERROR @  13925577 ps: (keymgr_csr_assert_fpv.sv:414) [ASSERT FAILED] sealing_sw_binding_4_rd_A
        UVM_INFO @  13925577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_same_csr_outstanding has 1 failures.

    • 0.keymgr_same_csr_outstanding.5153359024964246516964575910293095179468037559282108520955290941158530291386
      Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
        UVM_ERROR @ 144677948 ps: (keymgr_csr_assert_fpv.sv:459) [ASSERT FAILED] attest_sw_binding_5_rd_A
        UVM_INFO @ 144677948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.keymgr_csr_mem_rw_with_rand_reset.94877844658827252213370657368889097476092473260764768508252010401632808272015
      Line 86, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
        UVM_ERROR @  65647338 ps: (keymgr_csr_assert_fpv.sv:429) [ASSERT FAILED] sealing_sw_binding_7_rd_A
        UVM_INFO @  65647338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---