KMAC/MASKED Simulation Results

Wednesday May 21 2025 17:01:47 UTC

GitHub Revision: d7d3545

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	19.810s	704.141us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.790s	62.849us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.930s	60.378us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.190s	148.356us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.280s	457.720us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.500s	94.936us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.930s	60.378us	1	1	100.00
		kmac_csr_aliasing	7.280s	457.720us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.820s	13.667us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.130s	55.015us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.790s	42.281us	0	1	0.00
V2	burst_write	kmac_burst_write	19.889m	115.743ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.560s	10.156ms	1	1	100.00
		kmac_test_vectors_sha3_256	29.682m	232.060ms	1	1	100.00
		kmac_test_vectors_sha3_384	25.780s	3.925ms	1	1	100.00
		kmac_test_vectors_sha3_512	18.310s	1.116ms	1	1	100.00
		kmac_test_vectors_shake_128	3.498m	91.133ms	1	1	100.00
		kmac_test_vectors_shake_256	5.969m	96.262ms	1	1	100.00
		kmac_test_vectors_kmac	3.180s	426.866us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.640s	48.249us	1	1	100.00
V2	sideload	kmac_sideload	42.810s	12.681ms	1	1	100.00
V2	app	kmac_app	56.540s	11.377ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.570m	19.879ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	50.770s	3.020ms	1	1	100.00
V2	error	kmac_error	2.085m	3.035ms	1	1	100.00
V2	key_error	kmac_key_error	3.320s	1.180ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.080s	674.080us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	26.090s	10.970ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.700s	50.650us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	15.150s	1.896ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	7.950s	485.036us	1	1	100.00
V2	stress_all	kmac_stress_all	32.386m	149.678ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.860s	23.526us	1	1	100.00
V2	alert_test	kmac_alert_test	1.810s	120.651us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.240s	102.146us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.240s	102.146us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.790s	62.849us	1	1	100.00
		kmac_csr_rw	1.930s	60.378us	1	1	100.00
		kmac_csr_aliasing	7.280s	457.720us	1	1	100.00
		kmac_same_csr_outstanding	2.910s	193.445us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.790s	62.849us	1	1	100.00
		kmac_csr_rw	1.930s	60.378us	1	1	100.00
		kmac_csr_aliasing	7.280s	457.720us	1	1	100.00
		kmac_same_csr_outstanding	2.910s	193.445us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.180s	61.979us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.180s	61.979us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.180s	61.979us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.180s	61.979us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.920s	48.012us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	45.510s	4.444ms	1	1	100.00
		kmac_tl_intg_err	4.210s	197.564us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.210s	197.564us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	7.950s	485.036us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	19.810s	704.141us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	42.810s	12.681ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.180s	61.979us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	45.510s	4.444ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	45.510s	4.444ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	45.510s	4.444ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	19.810s	704.141us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	7.950s	485.036us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	45.510s	4.444ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.502m	24.169ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	19.810s	704.141us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	54.470s	2.428ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:

  • Test kmac_long_msg_and_output has 1 failures.

    • 0.kmac_long_msg_and_output.8258827027435008061268265415298373782735163377752632552627849509349861447441
      Line 72, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_long_msg_and_output/latest/run.log

        UVM_ERROR @  42281231 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @  42281231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.39971852909349656205299682544610265007788661289159563215626587809315285732948
      Line 126, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2427992604 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 2427992604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---